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| 8 bit microcontroller tlcs-870/c series TMP86FH47AUG
? 2010 toshiba corporation all rights reserved difference among product (tmp86xx46 series) 86c846 86ch46 86ch46a 86cm46 86cm46a 86ph46 86pm46 86pm46a 86fh46 86fh46a 86fh46b rom 8192bytes (mask) 16384bytes (mask) 32768bytes (mask) 16384bytes (otp) 32768bytes (otp) 16384bytes (flash) ram 512bytes 512bytes 1024bytes 512bytes 1024bytes 512bytes 512bytes dbr(note1) - 128bytes (flash con- trol register con- tained) i/o 33pins large current out- put 19pins (led direct drive) interrupt 18interrupt sources (external : 6 internal : 12) timer counter 16-bit timer counter : 1ch 8-bit timer counter : 2ch uart 8-bit uart : 1ch sio high-speed sio : 1ch key-on wakeup 4ch 10-bit ad converter analog-input : 8ch structure of test pin 86fh46a 86fh46b structure of xtin,xtout 86fh46a 86fh46b structure of p2 port 86fh46a 86fh46b TMP86FH47AUG fs rf r o osc. enable xtin xten xtout vdd vdd r without pull down resister without protect diode on the vdd side r vdd without pull down resister initial "high-z" input from output latch data output pin input r fs rf r o osc. enable xtin xten xtout vdd r in r vdd r in r fs rf r o osc. enable xtin xten xtout vdd vdd 86c846 86ch46 86ch46a 86cm46 86cm46a 86ph46 86pm46 86pm46a 86fh46 86fh46a 86fh46b number of guaran- teed writes to flash memory - - 100 times (a)86fh46b 1000 times (b)86fh46a 100 times terminal for seri- al prom mode (note2) - boot1/rxd(p10) boot2/txd(p11) boot/rxd(p02) txd(p03) emulation chip tmp86c947xb package sdip42-p-600-1.78 note 1: the products with flash memory (86fh46,86fh46a,86fh46b) contain the flash control register (flscr) at 0fffh in the dbr area. the products with mask rom or otp and the emulation chip do not have the flscr register. in these devices,therefore, a program that accesses the flscr register cannot function properly (executes differently as in the case of a flash product). note 2: the txd and rxd pins to be used in serial prom mode differ between the 86fh46 and the 86fh46a,86fh46b. take this into consideration in your board design when you replace the product. details of the function refer to the chapter of the 86fh46,86fh46a,86fh46b data sheet. note 3: p21,p22 combine xtin,xtout and port. TMP86FH47AUG difference among product (tmp86xx47 series) 86c847 86ch47 86ch47a 86cm47 86cm47a 86ph47 86pm47 86pm47a 86fh47 86fh47a 86fh47b rom 8192bytes (mask) 16384bytes (mask) 32768bytes (mask) 16384bytes (otp) 32768bytes (otp) 16384bytes (flash) ram 512bytes 512bytes 1024bytes 512bytes 1024bytes 512bytes 512bytes dbr(note1) - 128bytes (flash con- trol register con- tained) i/o 35pins large current out- put 19pins (led direct drive) interrupt 18interrupt sources (external : 6 internal : 12) timer counter 16-bit timer counter : 1ch 8-bit timer counter : 2ch uart 8-bit uart : 1ch sio high-speed sio : 1ch key-on wakeup 4ch 10-bit ad converter analog-input : 8ch structure of test pin 86fh47a 86fh47b structure of xtin,xtout 86fh47a 86fh47b structure of p2 port 86fh47a 86fh47b TMP86FH47AUG fs rf r o osc. enable xtin xten xtout vdd vdd r without pull down resister without protect diode on the vdd side r vdd without pull down resister initial "high-z" input from output latch data output pin input r fs rf r o osc. enable xtin xten xtout vdd r in r vdd r in r fs rf r o osc. enable xtin xten xtout vdd vdd 86c847 86ch47 86ch47a 86cm47 86cm47a 86ph47 86pm47 86pm47a 86fh47 86fh47a 86fh47b number of guaran- teed writes to flash memory - - 100 times (a)86fh47b 1000 times (b)86fh47a 100 times terminal for seri- al prom mode (note2) - boot1/rxd(p10) boot2/txd(p11) boot/rxd(p02) txd(p03) emulation chip tmp86c947xb package (lqfp44- p-1010-0.80a) available available (86ch47) available n.a. available available n.a. package (lqfp44- p-1010-0.80b) n.a. available (86ch47a) n.a. available n.a. n.a. available note 1: the products with flash memory (86fh47,86fh47a,86fh47b) contain the flash control register (flscr) at 0fffh in the dbr area. the products with mask rom or otp and the emulation chip do not have the flscr register. in these devices,therefore, a program that accesses the flscr register cannot function properly (executes differently as in the case of a flash product). note 2: the txd and rxd pins to be used in serial prom mode differ between the 86fh47 and the 86fh47a,86fh47b. take this into consideration in your board design when you replace the product. details of the function refer to the chapter of the 86fh47,86fh47a,86fh47b data sheet. note 3: p21,p22 combine xtin,xtout and port. TMP86FH47AUG differences in electrical characteristics (tmp86xx46 series) 86c846 / 86ch46 / 86cm46 86cm46a 86pm46 86ph46 86ch46a 86fh46 86fh46a 86fh46b operat- ing con- dition (mcu mode) read/ fetch (a) 1.8v to 5.5v (-40 to 85 c) (a) 2.0v to 5.5v (-40 to 85 c) (b) 1.8v to 2.0v (-20 to 85 c) (a) 2.7v to 5.5v (-40 to 85 c) tmp86fh46a (a) 3.0v to 5.5v (-40 to 85 c) (b) 2.7v to 3.0v (-20 to 85 c) tmp86fh46b (a) 2.7v to 5.5v (-40 to 85 c) erase/ pro- gram - - - (a) 4.5v to 5.5v (-10 to 40 c) operating condition (serial prom mode) - - (a) 4.5v to 5.5v (20 to 30 c) (a) 4.5v to 5.5v (-10 to 40 c) supply voltage (absolute maximum ratings) ?0.3 6.5 86fh46a (a)?0.3 6.5 86fh46b (a)?0.3 6.0 operating current operating current varies with each product. for details, refer to the datacheet (electrical chracteristics) of each product. (note3) note 1: with the 86ch46a,ph46 the operating temperature (topr) is -20 c to 85 c when the supply voltage vdd is less than 2.0v. note 2: with the 86fh46a, the operating temperature (topr) is -20 c to 85 c when the supply voltage vdd is less than 3.0v. note 3: with the 86fh46a,86fh46b when a program is executing in the flash memory or when data is being read from the flash memory, the flash memory operates in an intermittent manner causing peak currents in the flash memory momentarily, as shown in figure. in this case, the supply current idd(in normal1,normal2 and slow1 mode) is defined as the sum of the average peak current and mcu current. TMP86FH47AUG 5.5 4.5 2.7 1.8 0.030 0.034 2 4 8 16 [mhz] [v] (a) 5.5 4.5 2.7 1.8 2.0 0.030 0.034 1 4.2 8 16 [mhz] [v] (a) (b) (note1) 5.5 4.5 3.0 2.7 1.8 0.030 0.034 1 4.2 8 16 (a) (b) (note2) [mhz] [v] 5.5 4.5 2.7 1.8 0.030 0.034 2 4.2 8 16 [mhz] [v] (a) 5.5 4.5 2.7 1.8 0.030 0.034 1 4.2 8 16 [mhz] [v] (a) 5.5 4.5 2.7 1.8 0.030 0.034 1 4.2 8 16 [mhz] [v] (a) 5.5 4.5 2.7 1.8 0.030 0.034 1 4.2 8 16 [mhz] [v] (a) TMP86FH47AUG n program counter (pc) n+1 n+2 n+3 1 machine cycle (4/fc or 4/fs) mcu current i [ma] ddp-p typ. current momentary flash current max. current sum of average momentary flash current and mcu curren t intermittent operat ion of flash memory differences in electrical characteristics (tmp86xx47 series) 86c847 / 86ch47 / 86cm47 86cm47a 86pm47 86ph47 86ch47a 86fh47 86fh47a 86fh47b operat- ing con- dition (mcu mode) read/ fetch (a) 1.8v to 5.5v (-40 to 85 c) (a) 2.0v to 5.5v (-40 to 85 c) (b) 1.8v to 2.0v (-20 to 85 c) (a) 2.7v to 5.5v (-40 to 85 c) 86fh47a (a) 3.0v to 5.5v (-40 to 85 c) (b) 2.7v to 3.0v (-20 to 85 c) 86fh47b (a) 2.7v to 5.5v (-40 to 85 c) erase/ pro- gram - - - (a) 4.5v to 5.5v (-10 to 40 c) operating condition (serial prom mode) - - (a) 4.5v to 5.5v (20 to 30 c) (a) 4.5v to 5.5v (-10 to 40 c) supply voltage (absolute maximum ratings) ?0.3 6.5 86fh47a (a)?0.3 6.5 86fh47b (a)?0.3 6.0 operating current operating current varies with each product. for details, refer to the datacheet (electrical chracteristics) of each product. (note3) note 1: with the 86ch47a, ph47 the operating temperature (topr) is -20 c to 85 c when the supply voltage vdd is less than 2.0v. note 2: with the 86fh47a, the operating temperature (topr) is -20 c to 85 c when the supply voltage vdd is less than 3.0v. note 3: with the 86fh47a,86fh47b when a program is executing in the flash memory or when data is being read from the flash memory, the flash memory operates in an intermittent manner causing peak currents in the flash memory momentarily, as shown in figure. in this case, the supply current idd(in normal1,normal2 and slow1 mode) is defined as the sum of the average peak current and mcu current. TMP86FH47AUG 5.5 4.5 2.7 1.8 0.030 0.034 2 4 8 16 [mhz] [v] (a) 5.5 4.5 2.7 1.8 2.0 0.030 0.034 1 4.2 8 16 [mhz] [v] (a) (b) (note1) 5.5 4.5 3.0 2.7 1.8 0.030 0.034 1 4.2 8 16 (a) (b) (note2) [mhz] [v] 5.5 4.5 2.7 1.8 0.030 0.034 2 4.2 8 16 [mhz] [v] (a) 5.5 4.5 2.7 1.8 0.030 0.034 1 4.2 8 16 [mhz] [v] (a) 5.5 4.5 2.7 1.8 0.030 0.034 1 4.2 8 16 [mhz] [v] (a) 5.5 4.5 2.7 1.8 0.030 0.034 1 4.2 8 16 [mhz] [v] (a) TMP86FH47AUG n program counter (pc) n+1 n+2 n+3 1 machine cycle (4/fc or 4/fs) mcu current i [ma] ddp-p typ. current momentary flash current max. current sum of average momentary flash current and mcu curren t intermittent operat ion of flash memory revision history date revision 2006/2/22 1 first release 2006/6/29 2 periodical updating.no change in contents. 2006/10/4 3 contents revised 2010/10/7 4 contents revised table of contents difference among product (tmp86xx46 series) TMP86FH47AUG 1.1 features...................................................................................................................................... 1 1.2 pin assignment.......................................................................................................................... 3 1.3 block diagram........................................................................................................................... 4 1.4 pin names and functions.......................................................................................................... 5 2. operational description 2.1 cpu core functions ................................................................................................................. 7 2.1.1 memory address map ........................................................................................................................................................ 7 2.1.2 program memory (flash) .................................................................................................................................................... 7 2.1.3 data memory (ram) ......................................................................................................................................................... 7 2.2 system clock controller ........................................................................................................... 8 2.2.1 clock generator .................................................................................................................................................................. 8 2.2.2 timing generator .............................................................................................................................................................. 10 2.2.2.1 configuration of timing generator 2.2.2.2 machine cycle 2.2.3 operation mode control circuit ....................................................................................................................................... 11 2.2.3.1 single-clock mode 2.2.3.2 dual-clock mode 2.2.3.3 stop mode 2.2.4 operating mode control ................................................................................................................................................... 16 2.2.4.1 stop mode 2.2.4.2 idle1/2 mode and sleep1/2 mode 2.2.4.3 idle0 and sleep0 modes (idle0, sleep0) 2.2.4.4 slow mode 2.3 reset circuit ........................................................................................................................... 29 2.3.1 external reset input .......................................................................................................................................................... 29 2.3.2 address trap reset .............................................................................................................................................................. 30 2.3.3 watchdog timer reset ........................................................................................................................................................ 30 2.3.4 system clock reset ............................................................................................................................................................ 30 3. interrupt control circuit 3.1 interrupt latches (il15 to il2) ................................................................................................ 31 3.2 interrupt enable register (eir) ................................................................................................ 32 3.2.1 interrupt master enable flag (imf) ................................................................................................................................... 32 3.2.2 individual interrupt enable flags (ef15 to ef4) ............................................................................................................... 32 3.3 interrupt source selector (intsel)........................................................................................ 35 3.4 interrupt sequence ................................................................................................................. 35 3.4.1 interrupt acceptance processing is packaged as follows. .................................................................................................. 35 3.4.2 saving/restoring general-purpose registers ....................................................................................................................... 36 3.4.2.1 using push and pop instructions 3.4.2.2 using data transfer instructions 3.4.3 interrupt return .................................................................................................................................................................. 38 i 3.5 software interrupt (intsw) ................................................................................................... 39 3.5.1 address error detection ..................................................................................................................................................... 39 3.5.2 debugging .........................................................................................................................................................................39 3.6 undefined instruction interrupt (intundef) ...................................................................... 39 3.7 address trap interrupt (intatrap) .................................................................................... 39 3.8 external interrupts .................................................................................................................. 39 4. special function register (sfr) 4.1 sfr.......................................................................................................................................... 43 4.2 dbr......................................................................................................................................... 45 5. time base timer (tbt) 5.1 time base timer..................................................................................................................... 47 5.1.1 configuration..................................................................................................................................................................... 47 5.1.2 control............................................................................................................................................................................... 47 5.1.3 function............................................................................................................................................................................. 48 5.2 divider output (dvo).............................................................................................................49 5.2.1 configuration..................................................................................................................................................................... 49 5.2.2 control............................................................................................................................................................................... 49 6. watchdog timer (wdt) 6.1 watchdog timer configuration ..............................................................................................51 6.2 watchdog timer control ........................................................................................................ 52 6.2.1 malfunction detection methods using the watchdog timer .......................................................................................... 52 6.2.2 watchdog timer enable ................................................................................................................................................... 53 6.2.3 watchdog timer disable .................................................................................................................................................. 54 6.2.4 watchdog timer interrupt (intwdt) ............................................................................................................................. 54 6.2.5 watchdog timer reset ..................................................................................................................................................... 55 6.3 address trap ...........................................................................................................................56 6.3.1 selection of address trap in internal ram (atas) ....................................................................................................... 56 6.3.2 selection of operation at address trap (atout) .......................................................................................................... 56 6.3.3 address trap interrupt (intatrap)............................................................................................................................... 56 6.3.4 address trap reset............................................................................................................................................................ 57 7. i/o ports 7.1 port p0 (p07 to p00)................................................................................................................ 60 7.2 port p1 (p17 to p10)................................................................................................................ 61 7.3 port p2 (p22 to p20)................................................................................................................ 62 7.4 port p3 (p37 to p30)................................................................................................................ 63 7.5 port p4 (p47 to p40)................................................................................................................ 65 8. 16-bit timer/counter 1 (tc1) 8.1 configuration........................................................................................................................... 67 8.2 timer/counter control............................................................................................................ 68 ii 8.3 function................................................................................................................................... 70 8.3.1 timer mode........................................................................................................................................................................ 70 8.3.2 external trigger timer mode............................................................................................................................................72 8.3.3 event counter mode..........................................................................................................................................................74 8.3.4 window mode................................................................................................................................................................... 75 8.3.5 pulse width measurement mode.......................................................................................................................................76 8.3.6 programmable pulse generate (ppg) output mode......................................................................................................... 79 9. 8-bit timercounter (tc3, tc4) 9.1 configuration .......................................................................................................................... 83 9.2 timercounter control............................................................................................................. 84 9.3 function................................................................................................................................... 89 9.3.1 8-bit timer mode (tc3 and 4).......................................................................................................................................... 89 9.3.2 8-bit event counter mode (tc3, 4).................................................................................................................................. 90 9.3.3 8-bit programmable divider output (pdo) mode (tc3, 4)............................................................................................. 90 9.3.4 8-bit pulse width modulation (pwm) output mode (tc3, 4)........................................................................................ 93 9.3.5 16-bit timer mode (tc3 and 4)........................................................................................................................................ 95 9.3.6 16-bit event counter mode (tc3 and 4).......................................................................................................................... 96 9.3.7 16-bit pulse width modulation (pwm) output mode (tc3 and 4)................................................................................. 96 9.3.8 16-bit programmable pulse generate (ppg) output mode (tc3 and 4).......................................................................... 99 9.3.9 warm-up counter mode................................................................................................................................................. 101 9.3.9.1 low-frequency warm-up counter mode (normal1 normal2 slow2 slow1) 9.3.9.2 high-frequency warm-up counter mode (slow1 slow2 normal2 normal1) 10. synchronous serial interface (sio) 10.1 configuration ...................................................................................................................... 103 10.2 control................................................................................................................................. 104 10.3 function............................................................................................................................... 106 10.3.1 serial clock.................................................................................................................................................................... 106 10.3.1.1 clock source 10.3.1.2 shift edge 10.3.2 transfer bit direction..................................................................................................................................................... 108 10.3.2.1 transmit mode 10.3.2.2 receive mode 10.3.2.3 transmit/receive mode 10.3.3 transfer modes.............................................................................................................................................................. 109 10.3.3.1 transmit mode 10.3.3.2 receive mode 10.3.3.3 transmit/receive mode 11. asynchronous serial interface (uart) 11.1 configuration ...................................................................................................................... 121 11.2 control ................................................................................................................................ 122 11.3 transfer data format...........................................................................................................125 11.4 transfer rate....................................................................................................................... 126 11.5 data sampling method........................................................................................................ 126 11.6 stop bit length................................................................................................................. 127 11.7 parity.................................................................................................................................... 127 11.8 transmit/receive operation................................................................................................ 127 11.8.1 data transmit operation............................................................................................................................................... 127 11.8.2 data receive operation................................................................................................................................................. 127 iii 11.9 status flag........................................................................................................................... 128 11.9.1 parity error.................................................................................................................................................................... 128 11.9.2 framing error................................................................................................................................................................ 128 11.9.3 overrun error................................................................................................................................................................. 128 11.9.4 receive data buffer full............................................................................................................................................... 129 11.9.5 transmit data buffer empty......................................................................................................................................... 129 11.9.6 transmit end flag......................................................................................................................................................... 130 12. 10-bit ad converter (adc) 12.1 configuration ...................................................................................................................... 131 12.2 register configuration......................................................................................................... 132 12.3 function.............................................................................................................................. 135 12.3.1 software start mode...................................................................................................................................................... 135 12.3.2 repeat mode.................................................................................................................................................................. 135 12.3.3 register setting............................................................................................................................................................. 136 12.4 stop/slow modes during ad conversion...................................................................... 137 12.5 analog input voltage and ad conversion result.............................................................. 138 12.6 precautions about ad converter......................................................................................... 139 12.6.1 analog input pin voltage range...................................................................................................................................... 139 12.6.2 analog input shared pins............................................................................................................................................... 139 12.6.3 noise countermeasure................................................................................................................................................... 139 13. key-on wakeup (kwu) 13.1 configuration....................................................................................................................... 141 13.2 control................................................................................................................................. 141 13.3 function............................................................................................................................... 141 14. flash memory 14.1 flash memory control......................................................................................................... 144 14.1.1 flash memory command sequence execution control (flscr 15.3 serial prom mode setting................................................................................................. 154 15.3.1 serial prom mode control pins.................................................................................................................................. 154 15.3.2 pin function................................................................................................................................................................... 154 15.3.3 example connection for on-board writing..................................................................................................................155 15.3.4 activating the serial prom mode................................................................................................................................156 15.4 interface specifications for uart...................................................................................... 157 15.5 operation command............................................................................................................158 15.6 operation mode................................................................................................................... 158 15.6.1 flash memory erasing mode (operating command: f0h)........................................................................................... 160 15.6.2 flash memory writing mode (operation command: 30h)........................................................................................... 162 15.6.3 ram loader mode (operation command: 60h)......................................................................................................... 165 15.6.4 flash memory sum output mode (operation command: 90h).................................................................................. 167 15.6.5 product id code output mode (operation command: c0h)....................................................................................... 168 15.6.6 flash memory status output mode (operation command: c3h)................................................................................ 169 15.6.7 flash memory security program setting mode (operation command: fah).............................................................. 170 15.7 error code........................................................................................................................... 172 15.8 checksum (sum)................................................................................................................ 172 15.8.1 calculation method........................................................................................................................................................ 172 15.8.2 calculation data............................................................................................................................................................. 173 15.9 intel hex format (binary)................................................................................................... 174 15.10 passwords.......................................................................................................................... 174 15.10.1 password string........................................................................................................................................................... 175 15.10.2 handling of password error........................................................................................................................................ 175 15.10.3 password management during program development............................................................................................... 175 15.11 product id code................................................................................................................ 176 15.12 flash memory status code................................................................................................176 15.13 specifying the erasure area.............................................................................................. 178 15.14 port input control register................................................................................................178 15.15 flowchart........................................................................................................................... 180 15.16 uart timing....................................................................................................................181 16. input/output circuitry 16.1 control pins......................................................................................................................... 183 16.2 input/output ports............................................................................................................... 184 17. electrical characteristics 17.1 absolute maximum ratings................................................................................................ 185 17.2 operating conditions........................................................................................................... 186 17.2.1 serial prom mode........................................................................................................................................................ 186 17.2.2 mcu mode (except flash programming or erasing) ................................................................................................... 186 17.2.3 mcu mode (flash programming or erasing) ............................................................................................................... 187 17.3 dc characteristics............................................................................................................... 188 17.4 ad characteristics............................................................................................................... 190 17.5 ac characteristics............................................................................................................... 192 17.6 flash characteristics............................................................................................................ 193 17.6.1 write characteristics...................................................................................................................................................... 193 17.7 oscillating conditions......................................................................................................... 194 17.8 handling precaution............................................................................................................ 194 v 18. package dimensions vi cmos 8-bit microcontroller TMP86FH47AUG the TMP86FH47AUG is a single-chip 8-bit high-speed and high-functionality microcomputer incorporating 16384 bytes of flash memory. it is pin-compatible with the tmp86ch47aug/tmp86c847ug (mask rom version). the TMP86FH47AUG can realize operations equivalent to those of the tmp86ch47aug/tmp86c847ug by program- ming the on-chip flash memory. product no. rom (flash) ram package mask rom mcu emulation chip TMP86FH47AUG 16384 bytes 512 bytes p-lqfp44-1010-0.80b tmp86ch47aug/ tmp86c847ug tmp86c947xb 1.1 features 1. 8-bit single chip microcomputer tlcs-870/c series - instruction execution time : 0.25 s (at 16 mhz) 122 s (at 32.768 khz) - 132 types & 731 basic instructions 2. 18interrupt sources (external : 6 internal : 12) 3. input / output ports (35 pins) large current output: 19pins (typ. 20ma), led direct drive 4. prescaler - time base timer - divider output function 5. watchdog timer 6. 16-bit timer counter: 1 ch - timer, external trigger, window, pulse width measurement, event counter, programmable pulse generate (ppg) modes 7. 8-bit timer counter : 2 ch - timer, event counter, programmable divider output (pdo), pulse width modulation (pwm) output, programmable pulse generation (ppg), 16bit mode (8bit timer 2ch combination) modes 8. serial interface - high-speed 8-bit sio: 1ch 9. 8-bit uart : 1 ch 10. 10-bit successive approximation type ad converter - analog input: 8 ch 11. key-on wakeup : 4 ch 12. clock operation single clock mode dual clock mode this product uses the super flash? technology under the licence of silicon storage technology, inc. super flash? is registered trademark of silicon storage technology, inc. TMP86FH47AUG page 1 13. low power consumption operation stop mode: oscillation stops. (battery/capacitor back-up.) slow1 mode: low power consumption operation using low-frequency clock.(high-frequency clock stop.) slow2 mode: low power consumption operation using low-frequency clock.(high-frequency clock os- cillate.) idle0 mode: cpu stops, and only the time-based-timer(tbt) on peripherals operate using high fre- quency clock. release by falling edge of the source clock which is set by tbtcr 1.2 pin assignment p37 (ain7/stop5) p36 (ain6/stop4) p35 (ain5/stop3) p34 (ain4/stop2) p33 (ain3) p32 (ain2) p31 (ain1) p30 (ain0) p10 ( pdo3/pwm3/tc3) p11 (int1) p12 (int2/tc1) varef p13 ( dvo) avdd p14 ( ppg) avss p15 (int3) p40 p16 p41 p17 p42 p07 (int4) p43 p06 ( sck) p44 p05 (si) p45 p04 (so) p46 p03 (txd) p47 p02 (rxd/boot) vss xin xout test vdd (xtin) p21 (xtout) p22 reset ( int5/ stop) p20 ( int0) p00 ( pdo4/pwm4/ppg4/tc4) p01 figure 1-1 pin assignment TMP86FH47AUG page 3 1.3 block diagram figure 1-2 block diagram TMP86FH47AUG 1.3 block diagram page 4 1.4 pin names and functions the TMP86FH47AUG has mcu mode, parallel prom mode, and serial prom mode. table 1-1 shows the pin functions in mcu mode. the serial prom mode is explained later in a separate chapter. table 1-1 pin names and functions(1/3) pin name pin number input/output functions p07 int4 17 io i port07 external interrupt 4 input p06 sck 16 io io port06 serial clock input/output p05 si 15 io i port05 serial data input p04 so 14 io o port04 serial data output p03 txd 13 io o port03 uart data output p02 rxd boot 12 io i i port02 uart data input serial prom mode control input p01 tc4 pdo4/pwm4/ppg4 11 io i o port01 tc4 input pdo4/pwm4/ppg4 output p00 int0 10 io i port00 external interrupt 0 input p17 18 io port17 p16 19 io port16 p15 int3 20 io i port15 external interrupt 3 input p14 ppg 21 io o port14 ppg output p13 dvo 22 io o port13 divider output p12 int2 tc1 23 io i i port12 external interrupt 2 input tc1 input p11 int1 24 io i port11 external interrupt 1 input p10 pdo3/pwm3 tc3 25 io o i port10 pdo3/pwm3 output tc3 input p22 xtout 7 io o port22 resonator connecting pins(32.768khz) for inputting external clock p21 xtin 6 io i port21 resonator connecting pins(32.768khz) for inputting external clock TMP86FH47AUG page 5 table 1-1 pin names and functions(2/3) pin name pin number input/output functions p20 stop int5 9 io i i port20 stop mode release signal input external interrupt 5 input p37 ain7 stop5 33 io i i port37 analog input7 stop5 input p36 ain6 stop4 32 io i i port36 analog input6 stop4 input p35 ain5 stop3 31 io i i port35 analog input5 stop3 input p34 ain4 stop2 30 io i i port34 analog input4 stop2 input p33 ain3 29 io i port33 analog input3 p32 ain2 28 io i port32 analog input2 p31 ain1 27 io i port31 analog input1 p30 ain0 26 io i port30 analog input0 p47 44 io port47 p46 43 io port46 p45 42 io port45 p44 41 io port44 p43 40 io port43 p42 39 io port42 p41 38 io port41 p40 37 io port40 xin 2 i resonator connecting pins for high-frequency clock xout 3 o resonator connecting pins for high-frequency clock reset 8 io reset signal test 4 i test pin for out-going test. normally, be fixed to low. varef 34 i analog base voltage input pin for a/d conversion table 1-1 pin names and functions(3/3) pin name pin number input/output functions avdd 35 i analog power supply avss 36 i analog power supply vdd 5 i +5v vss 1 i 0(gnd) TMP86FH47AUG 1.4 pin names and functions page 6 2. operational description 2.1 cpu core functions the cpu core consists of a cpu, a system clock controller, and an interrupt controller. this section provides a description of the cpu core, the program memory, the data memory, and the reset circuit. 2.1.1 memory address map the TMP86FH47AUG memory is composed flash, ram, dbr(data buffer register) and sfr(special func- tion register). they are all mapped in 64-kbyte address space. figure 2-1 shows the TMP86FH47AUG memory address map. sfr 0000 h 64 bytes sfr: ram: special function register includes: i/o ports peripheral control registers peripheral status registers system control registers program status word random access memory includes: data memory stack 003f h ram 0040 h 512 bytes 023f h dbr 0f80 h 128 bytes dbr: data buffer register includes: peripheral control registers peripheral status registers 0fff h c000 h flash: program memory flash 16384 bytes ffc0 h vector table for vector call instructions (32 bytes) ffdf h ffe0 h vector table for interrupts (32 bytes) ffff h figure 2-1 memory address map 2.1.2 program memory (flash) the TMP86FH47AUG has a 16384 bytes (address c000h to ffffh) of program memory (flash). 2.1.3 data memory (ram) the TMP86FH47AUG has 512bytes (address 0040h to 023fh) of internal ram. the first 192 bytes (0040h to 00ffh) of the internal ram are located in the direct area; instructions with shorten operations are available against such an area. TMP86FH47AUG page 7 the data memory contents become unstable when the power supply is turned on; therefore, the data memory should be initialized by an initialization routine. example :clears ram to 00h. (TMP86FH47AUG) ld hl, 0040h ; start address setup ld a, h ; initial value (00h) setup ld bc, 01ffh sramclr: ld (hl), a inc hl dec bc jrs f, sramclr 2.2 system clock controller the system clock controller consists of a clock generator, a timing generator, and a standby controller. figure 2-2 system clock control 2.2.1 clock generator the clock generator generates the basic clock which provides the system clocks supplied to the cpu core and peripheral hardware. it contains two oscillation circuits: one for the high-frequency clock and one for the low- frequency clock. power consumption can be reduced by switching of the standby controller to low-power operation based on the low-frequency clock. the high-frequency (fc) clock and low-frequency (fs) clock can easily be obtained by connecting a resonator between the xin/xout and xtin/xtout pins respectively. clock input from an external oscillator is also possible. in this case, external clock is applied to xin/xtin pin with xout/xtout pin not connected. TMP86FH47AUG 2. operational description 2.2 system clock controller page 8 tbtcr syscr2 syscr1 xin xout xtin xtout fc 0036 h 0038 h 0039 h fs timing generator control register timing generator standby controller system clocks clock generator control high-frequency clock oscillator low-frequency clock oscillator clock generator system control registers figure 2-3 examples of resonator connection note:the function to monitor the basic clock directly at external is not provided for hardware, however, with disabling all interrupts and watchdog timers, the oscillation frequency can be adjusted by monitoring the pulse which the fixed frequency is outputted to the port by the program. the system to require the adjustment of the oscillation frequency should create the program for the adjustment in advance. TMP86FH47AUG page 9 xout xin (open) xout xin xtout xtin (open) xtout xtin (a) crystal/ceramic resonator (b) external oscillator (c) crystal (d) external oscillator high-frequency clock low-frequency clock 2.2.2 timing generator the timing generator generates the various system clocks supplied to the cpu core and peripheral hardware from the basic clock (fc or fs). the timing generator provides the following functions. 1. generation of main system clock 2. generation of divider output ( dvo) pulses 3. generation of source clocks for time base timer 4. generation of source clocks for watchdog timer 5. generation of internal source clocks for timer/counters 6. generation of warm-up clocks for releasing stop mode 2.2.2.1 configuration of timing generator the timing generator consists of a 2-stage prescaler, a 21-stage divider, a main system clock generator, and machine cycle counters. an input clock to the 7th stage of the divider depends on the operating mode, syscr2 timing generator control register tbtcr (0036h) 7 6 5 4 3 2 1 0 (dvoen) (dvock) dv7ck (tbten) (tbtck) (initial value: 0000 0000) dv7ck selection of input to the 7th stage of the divider 0: fc/2 8 [hz] 1: fs r/w note 1: in single clock mode, do not set dv7ck to 1. note 2: do not set 1 on dv7ck while the low-frequency clock is not operated stably. note 3: fc: high-frequency clock [hz], fs: low-frequency clock [hz], *: dont care note 4: in slow1/2 and sleep1/2 modes, the dv7ck setting is ineffective, and fs is input to the 7th stage of the divider. note 5: when stop mode is entered from normal1/2 mode, the dv7ck setting is ineffective during the warm-up period after release of stop mode, and the 6th stage of the divider is input to the 7th stage during this period. 2.2.2.2 machine cycle instruction execution and peripheral hardware operation are synchronized with the main system clock. the minimum instruction execution unit is called an machine cycle. there are a total of 10 different types of instructions for the tlcs-870/c series: ranging from 1-cycle instructions which require one machine cycle for execution to 10-cycle instructions which require 10 machine cycles for execution. a machine cycle consists of 4 states (s0 to s3), and each state consists of one main system clock. figure 2-5 machine cycle 2.2.3 operation mode control circuit the operation mode control circuit starts and stops the oscillation circuits for the high-frequency and low- frequency clocks, and switches the main system clock. there are three operating modes: single clock mode, dual clock mode and stop mode. these modes are controlled by the system control registers (syscr1 and syscr2). figure 2-6 shows the operating mode transition diagram. 2.2.3.1 single-clock mode only the oscillation circuit for the high-frequency clock is used, and p21 (xtin) and p22 (xtout) pins are used as input/output ports. the main-system clock is obtained from the high-frequency clock. in the single- clock mode, the machine cycle time is 4/fc [s]. (1) normal1 mode in this mode, both the cpu core and on-chip peripherals operate using the high-frequency clock. the TMP86FH47AUG is placed in this mode after reset. TMP86FH47AUG page 11 main system clock state machine cycle s3 s2 s1 s0 s3 s2 s1 s0 1/fc or 1/fs [s] (2) idle1 mode in this mode, the internal oscillation circuit remains active. the cpu and the watchdog timer are halted; however on-chip peripherals remain active (operate using the high-frequency clock). idle1 mode is started by syscr2 switching back and forth between slow1 and slow2 modes are performed by syscr2 note 1: normal1 and normal2 modes are generically called normal; slow1 and slow2 are called slow; idle0, idle1 and idle2 are called idle; sleep0, sleep1 and sleep2 are called sleep. note 2: the mode is released by falling edge of tbtcr system control register 1 syscr1 7 6 5 4 3 2 1 0 (0038h) stop relm retm outen wut (initial value: 0000 000*) stop stop mode start 0: cpu core and peripherals remain active 1: cpu core and peripherals are halted (start stop mode) r/w relm release method for stop mode 0: edge-sensitive release 1: level-sensitive release r/w retm operating mode after stop mode 0: return to normal1/2 mode 1: return to slow1 mode r/w outen port output during stop mode 0: high impedance 1: output kept r/w wut warm-up time at releasing stop mode return to normal mode return to slow mode r/w 000 010 100 110 *01 *11 3 x 2 16 /fc 2 16 /fc 3 x 2 14 /fc 2 14 /fc 3 x 2 10 /fc 2 10 /fc 3 x 2 13 /fs 2 13 /fs 3 x 2 6 /fs 2 6 /fs 3 x 2 6 /fs 2 6 /fs note 1: always set retm to 0 when transiting from normal mode to stop mode. always set retm to 1 when transiting from slow mode to stop mode. note 2: when stop mode is released with reset pin input, a return is made to normal1 regardless of the retm contents. note 3: fc: high-frequency clock [hz], fs: low-frequency clock [hz], *; dont care note 4: bits 1 in syscr1 are read as undefined data when a read instruction is executed. note 5: as the hardware becomes stop mode under outen = 0, input value is fixed to 0; therefore it may cause external interrupt request on account of falling edge. note 6: when the key-on wakeup is used, relm should be set to "1". note 7: port p20 is used as stop pin. therefore, when stop mode is started, outen does not affect to p20, and p20 becomes high-z mode. note 8: the warming-up time should be set correctly for using oscillator. system control register 2 syscr2 (0039h) 7 6 5 4 3 2 1 0 xen xten sysck idle tghalt (initial value: 1000 *0**) xen high-frequency oscillator control 0: turn off oscillation 1: turn on oscillation r/w xten low-frequency oscillator control 0: turn off oscillation 1: turn on oscillation sysck main system clock select (write)/ main system clock monitor (read) 0: high-frequency clock (normal1/normal2/idle1/idle2) 1: low-frequency clock (slow1/slow2/sleep1/sleep2) idle cpu and watchdog timer control (idle1/2 and sleep1/2 modes) 0: cpu and watchdog timer remain active 1: cpu and watchdog timer are stopped (start idle1 /2 and sleep1/2 modes) r/w tghalt tg control (idle0 and sleep0 modes) 0: feeding clock to all peripherals from tg 1: stop feeding clock to peripherals except tbt from tg (start idle0 and sleep0 modes) note 1: a reset is applied if both xen and xten are cleared to 0, xen is cleared to 0 when sysck = 0, or xten is cleared to 0 when sysck = 1. note 2: *: dont care, tg: timing generator, *; dont care note 3: bits 3, 1 and 0 in syscr2 are always read as undefined value. note 4: do not set idle and tghalt to 1 simultaneously. note 5: because returning from idle0/sleep0 to normal1/slow1 is executed by the asynchronous internal clock, the period of idle0/sleep0 mode might be shorter than the period setting by tbtcr note 6: when idle1/2 or sleep1/2 mode is released, idle is automatically cleared to 0. note 7: when idle0 or sleep0 mode is released, tghalt is automatically cleared to 0. note 8: before setting tghalt to 1, be sure to stop peripherals. if peripherals are not stopped, the interrupt latch of peripherals may be set after idle0 or sleep0 mode is released. 2.2.4 operating mode control 2.2.4.1 stop mode stop mode is controlled by the system control register 1, the stop pin input and key-on wakeup input (stop5 to stop2) which is controlled by the stop mode release control register (stopcr) . the stop pin is also used both as a port p20 and an int5 (external interrupt input 5) pin. stop mode is started by setting syscr1 example 2 :starting stop mode from normal mode with an int5 interrupt. pint5: test (p2prd). 0 ; to reject noise, stop mode does not start if jrs f, sint5 port p20 is at high ld (syscr1), 01010000b ; sets up the level-sensitive release mode. di ; imf 0 set (syscr1). 7 ; starts stop mode sint5: reti figure 2-7 level-sensitive release mode note 1: even if the stop pin input is low after warm-up start, the stop mode is not restarted. note 2: in this case of changing to the level-sensitive mode from the edge-sensitive mode, the release mode is not switched until a rising edge of the stop pin input is detected. (2) edge-sensitive release mode (relm = 0) in this mode, stop mode is released by a rising edge of the stop pin input. this is used in appli- cations where a relatively short program is executed repeatedly at periodic intervals. this periodic signal (for example, a clock from a low-power consumption oscillator) is input to the stop pin. in the edge- sensitive release mode, stop mode is started even when the stop pin input is high level. do not use any stop5 to stop2 pin input for releasing stop mode in edge-sensitive release mode. example :starting stop mode from normal mode di ; imf 0 ld (syscr1), 10010000b ; starts after specified to the edge-sensitive release mode figure 2-8 edge-sensitive release mode TMP86FH47AUG page 17 normal operation normal operation v ih stop mode is released by the hardware at the rising edge of stop pin input. warm up stop mode started by the program. stop operation stop operation stop pin xout pin v ih normal operation warm up stop operation confirm by program that the stop pin input is low and start stop mode. always released if the stop pin input is high. stop pin xout pin stop mode is released by the hardware. normal operation stop mode is released by the following sequence. 1. in the dual-clock mode, when returning to normal2, both the high-frequency and low- frequency clock oscillators are turned on; when returning to slow1 mode, only the low- frequency clock oscillator is turned on. in the single-clock mode, only the high-frequency clock oscillator is turned on. 2. a warm-up period is inserted to allow oscillation time to stabilize. during warm up, all internal operations remain halted. six different warm-up times can be selected with the syscr1 figure 2-9 stop mode start/release TMP86FH47AUG page 19 instruction address a + 4 0 instruction address a + 3 turn on turn on warm up 0 n halt set (syscr1). 7 turn off (a) stop mode start (example: start with set (syscr1). 7 instruction located at address a) a + 6 a + 5 a + 4 a + 3 a + 2 n + 2 n + 3 n + 4 a + 3 n + 1 instruction address a + 2 2 1 0 3 (b) stop mode release count up turn off halt oscillator circuit program counter instruction execution divider main system clock oscillator circuit stop pin input program counter instruction execution divider main system clock 2.2.4.2 idle1/2 mode and sleep1/2 mode idle1/2 and sleep1/2 modes are controlled by the system control register 2 (syscr2) and maskable interrupts. the following status is maintained during these modes. 1. operation of the cpu and watchdog timer (wdt) is halted. on-chip peripherals continue to operate. 2. the data memory, cpu registers, program status word and port output latches are all held in the status in effect before these modes were entered. 3. the program counter holds the address 2 ahead of the instruction which starts these modes. figure 2-10 idle1/2 and sleep1/2 modes TMP86FH47AUG 2. operational description 2.2 system clock controller page 20 reset reset input ?0? ?1? (interrupt release mode) yes no no cpu and wdt are halted interrupt request imf interrupt processing normal release mode yes starting idle1/2 and sleep1/2 modes by instruction execution of the instruc- tion which follows the idle1/2 and sleep1/2 modes start instruction ? start the idle1/2 and sleep1/2 modes after imf is set to "0", set the individual interrupt enable flag (ef) which releases idle1/2 and sleep1/2 modes. to start idle1/2 and sleep1/2 modes, set syscr2 figure 2-11 idle1/2 and sleep1/2 modes start/release 2.2.4.3 idle0 and sleep0 modes (idle0, sleep0) idle0 and sleep0 modes are controlled by the system control register 2 (syscr2) and the time base timer control register (tbtcr). the following status is maintained during idle0 and sleep0 modes. TMP86FH47AUG 2. operational description 2.2 system clock controller page 22 halt halt halt halt operate instruction address a + 2 a + 3 a + 2 a + 4 a + 3 a + 3 halt set (syscr2). 4 operate operate operate acceptance of interrupt ?r:w normal release mode ?s:w interrupt release mode main system clock interrupt request program counter instruction execution watchdog timer main system clock interrupt request program counter instruction execution watchdog timer main system clock interrupt request program counter instruction execution watchdog timer (a) idle1/2 and sleep1/2 modes start (example: star ting with the set instruction located at address a) (b) idle1/2 and sleep1/2 modes release 1. timing generator stops feeding clock to peripherals except tbt. 2. the data memory, cpu registers, program status word and port output latches are all held in the status in effect before idle0 and sleep0 modes were entered. 3. the program counter holds the address 2 ahead of the instruction which starts idle0 and sleep0 modes. note:before starting idle0 or sleep0 mode, be sure to stop (disable) peripherals. figure 2-12 idle0 and sleep0 modes TMP86FH47AUG page 23 yes (normal release mode) yes (interrupt release mode) no yes reset input cpu and wdt are halted reset tbt source clock falling edge tbtcr ? start the idle0 and sleep0 mode s stop (disable) peripherals such as a timer counter. to start idle0 and sleep0 mode s, set syscr2 figure 2-13 idle0 and sleep0 modes start/release 2.2.4.4 slow mode slow mode is controlled by the system control register 2 (syscr2). TMP86FH47AUG page 25 halt halt operate instruction address a + 2 halt operate set (syscr2). 2 halt operate acceptance of interrupt halt ?r:w normal release mode ?s:w interrupt release mode main system clock interrupt request program counter instruction execution watchdog timer main system clock tbt clock tbt clock program counter instruction execution watchdog timer main system clock program counter instruction execution watchdog timer a + 3 a + 2 a + 4 a + 3 a + 3 (a) idle0 and sleep0 modes start (example: starting with the set instruction located at address a (b) idle and sleep0 modes release the following is the methods to switch the mode with the warm-up counter. (1) switching from normal2 mode to slow1 mode first, set syscr2 (2) switching from slow1 mode to normal2 mode first, set syscr2 figure 2-14 switching between the normal2 and slow modes TMP86FH47AUG 2. operational description 2.2 system clock controller page 28 set (syscr2). 7 normal2 mode clr (syscr2). 7 set (syscr2). 5 normal2 mode turn off (a) switching to the slow mode slow1 mode slow2 mode clr (syscr2). 5 (b) switching to the normal2 mode high- frequency clock low- frequency clock main system clock instruction execution sysck xen high- frequency clock low- frequency clock main system clock instruction execution sysck xen slow1 mode warm up during slow2 mode 2.3 reset circuit the TMP86FH47AUG has four types of reset generation procedures: an external reset input, an address trap reset, a watchdog timer reset and a system clock reset. of these reset, the address trap reset, the watchdog timer and the system clock reset are a malfunction reset. when the malfunction reset request is detected, reset occurs during the maximum 24/fc[s] (the reset pin outputs "l" level). the malfunction reset circuit such as watchdog timer reset, address trap reset and system clock reset is not initialized when power is turned on. therefore, reset may occur during maximum 24/fc[s] (1.5s at 16.0 mhz) when power is turned on. reset pin outputs "l" level during maximum 24/fc[s] (1.5s at 16.0mhz). table 2-3 shows on-chip hardware initialization by reset action. table 2-3 initializing internal status by reset action on-chip hardware initial value on-chip hardware initial value program counter (pc) (fffeh) prescaler and divider of timing generator 0 stack pointer (sp) not initialized general-purpose registers (w, a, b, c, d, e, h, l, ix, iy) not initialized jump status flag (jf) not initialized watchdog timer enable zero flag (zf) not initialized output latches of i/o ports refer to i/o port circuitry carry flag (cf) not initialized half carry flag (hf) not initialized sign flag (sf) not initialized overflow flag (vf) not initialized interrupt master enable flag (imf) 0 interrupt individual enable flags (ef) 0 control registers refer to each of control register interrupt latches (il) 0 ram not initialized 2.3.1 external reset input the reset pin contains a schmitt trigger (hysteresis) with an internal pull-up resistor. when the reset pin is held at l level for at least 3 machine cycles (12/fc [s]) with the power supply voltage within the operating voltage range and oscillation stable, a reset is applied and the internal state is initialized. whenthe reset pin input goes high, the reset operation is released and the program execution starts at the vector address stored at addresses fffeh to ffffh. figure 2-15 reset circuit TMP86FH47AUG page 29 internal reset reset vdd malfunction reset output circuit watchdog timer reset address trap reset system clock reset 2.3.2 address trap reset if the cpu should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip ram (when wdtcr1 3. interrupt control circuit the TMP86FH47AUG has a total of 18 interrupt sources excluding reset, of which 2 source levels are multi- plexed. interrupts can be nested with priorities. four of the internal interrupt sources are non-maskable while the rest are maskable. interrupt sources are provided with interrupt latches (il), which hold interrupt requests, and independent vectors. the interrupt latch is set to 1 by the generation of its interrupt request which requests the cpu to accept its interrupts. interrupts are enabled or disabled by software using the interrupt master enable flag (imf) and interrupt enable flag (ef). if more than one interrupts are generated simultaneously, interrupts are accepted in order which is dominated by hardware. however, there are no prioritized interrupt factors among non-maskable interrupts. interrupt factors enable condition interrupt latch vector ad- dress priority internal/external (reset) non-maskable - fffe 1 internal intswi (software interrupt) non-maskable - fffc 2 internal intundef (executed the undefined instruction in- terrupt) non-maskable - fffc 2 internal intatrap (address trap interrupt) non-maskable il2 fffa 2 internal intwdt (watchdog timer interrupt) non-maskable il3 fff8 2 external int0 imf? ef4 = 1, int0en = 1 il4 fff6 5 external int1 imf? ef5 = 1 il5 fff4 6 internal inttbt imf? ef6 = 1 il6 fff2 7 internal inttc1 imf? ef7 = 1 il7 fff0 8 external int2 imf? ef8 = 1 il8 ffee 9 internal inttc4 imf? ef9 = 1 il9 ffec 10 internal inttc3 imf? ef10 = 1 il10 ffea 11 external int3 imf? ef11 = 1 il11 ffe8 12 internal intsio imf? ef12 = 1 il12 ffe6 13 internal intrxd imf? ef13 = 1 il13 ffe4 14 external int4 imf? ef14 = 1, il14er = 0 il14 ffe2 15 internal inttxd imf? ef14 = 1, il14er = 1 external int5 imf? ef15 = 1, il15er = 0 il15 ffe0 16 internal intadc imf? ef15 = 1, il15er = 1 note 1: the intsel register is used to select the interrupt source to be enabled for each multiplexed source level (see 3.3 interrupt source selector (intsel)). note 2: to use the address trap interrupt (intatrap), clear wdtcr1 since interrupt latches can be read, the status for interrupt requests can be monitored by software. note:in main program, before manipulating the interrupt enable flag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf newly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf becomes "0" automatically, clearing imf need not execute normally on interrupt service routine. however, if using multiple interrupt on interrupt service routine, manipulating ef or il should be executed before setting imf="1". example 1 :clears interrupt latches di ; imf 0 ldw (ill), 1110100000111111b ; il12, il10 to il6 0 ei ; imf 1 example 2 :reads interrupt latches ld wa, (ill) ; w ilh, a ill example 3 :tests interrupt latches test (ill). 7 ; if il7 = 1 then jump jr f, sset 3.2 interrupt enable register (eir) the interrupt enable register (eir) enables and disables the acceptance of interrupts, except for the non-maskable interrupts (software interrupt, undefined instruction interrupt, address trap interrupt and watchdog interrupt). non- maskable interrupt is accepted regardless of the contents of the eir. the eir consists of an interrupt master enable flag (imf) and the individual interrupt enable flags (ef). these registers are located on address 003ah and 003bh in sfr area, and they can be read and written by an instructions (including read-modify-write instructions such as bit manipulation or operation instructions). 3.2.1 interrupt master enable flag (imf) the interrupt enable register (imf) enables and disables the acceptance of the whole maskable interrupt. while imf = 0, all maskable interrupts are not accepted regardless of the status on each individual interrupt enable flag (ef). by setting imf to 1, the interrupt becomes acceptable if the individuals are enabled. when an interrupt is accepted, imf is cleared to 0 after the latest status on imf is stacked. thus the maskable interrupts which follow are disabled. by executing return interrupt instruction [reti/retn], the stacked data, which was the status before interrupt acceptance, is loaded on imf again. the imf is located on bit0 in eirl (address: 003ah in sfr), and can be read and written by an instruction. the imf is normally set and cleared by [ei] and [di] instruction respectively. during reset, the imf is initialized to 0. 3.2.2 individual interrupt enable flags (ef15 to ef4) each of these flags enables and disables the acceptance of its maskable interrupt. setting the corresponding bit of an individual interrupt enable flag to 1 enables acceptance of its interrupt, and setting the bit to 0 disables acceptance. during reset, all the individual interrupt enable flags (ef15 to ef4) are initialized to 0 and all maskable interrupts are not accepted until they are set to 1. note:in main program, before manipulating the interrupt enable flag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf newly again as required after operating on the ef or il (enable interrupt by ei instruction) TMP86FH47AUG 3. interrupt control circuit 3.2 interrupt enable register (eir) page 32 in interrupt service routine, because the imf becomes "0" automatically, clearing imf need not execute normally on interrupt service routine. however, if using multiple interrupt on interrupt service routine, manipulating ef or il should be executed before setting imf="1". example 1 :enables interrupts individually and sets imf di ; imf 0 ldw : (eirl), 1110100010100000b ; ef15 to ef13, ef11, ef7, ef5 1 note: imf should not be set. : ei ; imf 1 example 2 :c compiler description example unsigned int _io (3ah) eirl; /* 3ah shows eirl address */ _di(); eirl = 10100000b; : _ei(); interrupt latches (initial value: 00000000 000000**) ilh,ill (003dh, 003ch) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 il15 il14 il13 il12 il11 il10 il9 il8 il7 il6 il5 il4 il3 il2 ilh (003dh) ill (003ch) il15 to il2 interrupt latches at rd 0: no interrupt request 1: interrupt request at wr 0: clears the interrupt request 1: (interrupt latch is not set.) r/w note 1: to clear any one of bits il7 to il4, be sure to write "1" into il2 and il3. note 2: in main program, before manipulating the interrupt enable flag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf newly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf becomes "0" automatically, clearing imf need not execute normally on interrupt service routine. however, if using multiple interrupt on interrupt service routine, manipulating ef or il should be executed before setting imf="1". note 3: do not clear il with read-modify-write instructions such as bit operations. interrupt enable registers (initial value: 00000000 0000***0) eirh,eirl (003bh, 003ah) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ef15 ef14 ef13 ef12 ef11 ef10 ef9 ef8 ef7 ef6 ef5 ef4 imf eirh (003bh) eirl (003ah) ef15 to ef4 individual-interrupt enable flag (specified for each bit) 0: 1: disables the acceptance of each maskable interrupt. enables the acceptance of each maskable interrupt. r/w imf interrupt master enable flag 0: 1: disables the acceptance of all maskable interrupts enables the acceptance of all maskable interrupts note 1: *: dont care note 2: do not set imf and the interrupt enable flag (ef15 to ef4) to 1 at the same time. TMP86FH47AUG page 33 note 3: in main program, before manipulating the interrupt enable flag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf newly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf becomes "0" automatically, clearing imf need not execute normally on interrupt service routine. however, if using multiple interrupt on interrupt service routine, manipulating ef or il should be executed before setting imf="1". TMP86FH47AUG 3. interrupt control circuit 3.2 interrupt enable register (eir) page 34 3.3 interrupt source selector (intsel) each interrupt source that shares the interrupt source level with another interrupt source is allowed to enable the interrupt latch only when it is selected in the intsel register. the interrupt controller does not hold interrupt requests corresponding to interrupt sources that are not selected in the intsel register. therefore, the intsel register must be set appropriately before interrupt requests are generated. the following interrupt sources share their interrupt source level; the source is selected on the register intsel. 1. int4 and inttxd share the interrupt source level whose priority is 15. 2. int5 and intadc share the interrupt source level whose priority is 16. interrupt source selector intsel (003eh) 7 6 5 4 3 2 1 0 - - - - - - il14er il15er (initial value: **** **00) il14er selects int4 or inttxd 0: int4 1: inttxd r/w il15er selects int5 or intadc 0: int5 1: intadc r/w 3.4 interrupt sequence an interrupt request, which raised interrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to 0 by resetting or an instruction. interrupt acceptance sequence requires 8 machine cycles (2 s @16 mhz) after the completion of the current instruction. the interrupt service task terminates upon execution of an interrupt return instruction [reti] (for maskable interrupts) or [retn] (for non-maskable interrupts). figure 3-1 shows the timing chart of interrupt acceptance processing. 3.4.1 interrupt acceptance processing is packaged as follows. a. the interrupt master enable flag (imf) is cleared to 0 in order to disable the acceptance of any following interrupt. b. the interrupt latch (il) for the interrupt source accepted is cleared to 0. c. the contents of the program counter (pc) and the program status word, including the interrupt master enable flag (imf), are saved (pushed) on the stack in sequence of psw + imf, pch, pcl. meanwhile, the stack pointer (sp) is decremented by 3. d. the entry address (interrupt vector) of the corresponding interrupt service program, loaded on the vector table, is transferred to the program counter. e. the instruction stored at the entry address of the interrupt service program is executed. note:when the contents of psw are saved on the stack, the contents of imf are also saved. TMP86FH47AUG page 35 note 1: a: return address, b: entry address, c: address which reti instruction is stored note 2: on condition that interrupt is enabled, it takes 38/fc [s] or 38/fs [s] at maximum (if the interrupt latch is set at the first machine cycle on 10 cycle instruction) to start interrupt acceptance processing since its interrupt latch is set. figure 3-1 timing chart of interrupt acceptance/return interrupt instruction example: correspondence between vector table address for inttbt and the entry address of the interrupt service program figure 3-2 vector table address,entry address a maskable interrupt is not accepted until the imf is set to 1 even if the maskable interrupt higher than the level of current servicing interrupt is requested. in order to utilize nested interrupt service, the imf is set to 1 in the interrupt service program. in this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags. to avoid overloaded nesting, clear the individual interrupt enable flag whose interrupt is currently serviced, before setting imf to 1. as for non-maskable interrupt, keep interrupt service shorten compared with length between interrupt requests; otherwise the status cannot be recovered as non-maskable interrupt would simply nested. 3.4.2 saving/restoring general-purpose registers during interrupt acceptance processing, the program counter (pc) and the program status word (psw, includes imf) are automatically saved on the stack, but the accumulator and others are not. these registers are saved by software if necessary. when multiple interrupt services are nested, it is also necessary to avoid using the same data memory area for saving registers. the following methods are used to save/restore the general-purpose reg- isters. TMP86FH47AUG 3. interrupt control circuit 3.4 interrupt sequence page 36 d2h 03h d203h d204h 06h vector table address entry address 0fh vector interrupt service program fff2h fff3h a b a c + 1 execute instruction sp pc execute instruction n n ? 2 n - 3 n ? 2n ? 1 n ? 1 n a + 2 a + 1 c + 2 b + 3 b + 2 b + 1 a + 1 a a ? 1 execute reti instruction interrupt acceptance execute instruction interrupt service task 1-machine cycle interrupt request interrupt latch (il) imf 3.4.2.1 using push and pop instructions if only a specific register is saved or interrupts of the same source are nested, general-purpose registers can be saved/restored using the push/pop instructions. example :save/store register using push and pop instructions pintxx: push wa ; save wa register (interrupt processing) pop wa ; restore wa register reti ; return figure 3-3 save/store register using push and pop instructions 3.4.2.2 using data transfer instructions to save only a specific register without nested interrupts, data transfer instructions are available. example :save/store register using data transfer instructions pintxx: ld (gsava), a ; save a register (interrupt processing) ld a, (gsava) ; restore a register reti ; return TMP86FH47AUG page 37 pcl pch psw at acceptance of an interrupt at execution of push instruction at execution of reti instruction at execution of pop instruction b-4 b-3 b-2 b-1 b pcl pch psw pcl pch psw sp address (example) sp sp sp a w b-5 figure 3-4 saving/restoring general-purpose registers under interrupt processing 3.4.3 interrupt return interrupt return instructions [reti]/[retn] perform as follows. [reti]/[retn] interrupt return 1. program counter (pc) and program status word (psw, includes imf) are restored from the stack. 2. stack pointer (sp) is incremented by 3. as for address trap interrupt (intatrap), it is required to alter stacked data for program counter (pc) to restarting address, during interrupt service program. note:if [retn] is executed with the above data unaltered, the program returns to the address trap area and intatrap occurs again. when interrupt acceptance processing has completed, stacked data for pcl and pch are located on address (sp + 1) and (sp + 2) respectively. example 1 :returning from address trap interrupt (intatrap) service program pintxx: pop wa ; recover sp by 2 ld wa, return address ; push wa ; alter stacked data (interrupt processing) retn ; return example 2 :restarting without returning interrupt (in this case, psw (includes imf) before interrupt acceptance is discarded.) pintxx: inc sp ; recover sp by 3 inc sp ; inc sp ; (interrupt processing) ld eirl, data ; set imf to 1 or clear it to 0 jp restart address ; jump into restarting address interrupt requests are sampled during the final cycle of the instruction being executed. thus, the next interrupt can be accepted immediately after the interrupt return instruction is executed. note 1: it is recommended that stack pointer be return to rate before intatrap (increment 3 times), if return interrupt instruction [retn] is not utilized during interrupt service program under intatrap (such as example 2). TMP86FH47AUG 3. interrupt control circuit 3.4 interrupt sequence page 38 interrupt acceptance interrupt service task restoring registers saving registers interrupt return saving/restoring general-purpose registers using push/pop data transfer instruction main task note 2: when the interrupt processing time is longer than the interrupt request generation time, the interrupt service task is performed but not the main task. 3.5 software interrupt (intsw) executing the swi instruction generates a software interrupt and immediately starts interrupt processing (intsw is highest prioritized interrupt). use the swi instruction only for detection of the address error or for debugging. 3.5.1 address error detection ffh is read if for some cause such as noise the cpu attempts to fetch an instruction from a non-existent memory address during single chip mode. code ffh is the swi instruction, so a software interrupt is generated and an address error is detected. the address error detection range can be further expanded by writing ffh to unused areas of the program memory. address trap reset is generated in case that an instruction is fetched from ram, dbr or sfr areas. 3.5.2 debugging debugging efficiency can be increased by placing the swi instruction at the software break point setting address. 3.6 undefined instruction interrupt (intundef) taking code which is not defined as authorized instruction for instruction causes intundef. intundef is generated when the cpu fetches such a code and tries to execute it. intundef is accepted even if non-maskable interrupt is in process. contemporary process is broken and intundef interrupt process starts, soon after it is requested. note:the undefined instruction interrupt (intundef) forces cpu to jump into vector address, as software interrupt (swi) does. 3.7 address trap interrupt (intatrap) fetching instruction from unauthorized area for instructions (address trapped area) causes reset output or address trap interrupt (intatrap). intatrap is accepted even if non-maskable interrupt is in process. contemporary process is broken and intatrap interrupt process starts, soon after it is requested. note:the operating mode under address trapped, whether to be reset output or interrupt processing, is selected on watchdog timer control register (wdtcr). 3.8 external interrupts the TMP86FH47AUG has 6 external interrupt inputs. these inputs are equipped with digital noise reject circuits (pulse inputs of less than a certain time are eliminated as noise). edge selection is also possible with int1 to int4. the int0/p00 pin can be configured as either an external interrupt input pin or an input/output port, and is configured as an input port during reset. edge selection, noise reject control and int0/p00 pin function selection are performed by the external interrupt control register (eintcr). TMP86FH47AUG page 39 source pin enable conditions release edge (level) digital noise reject int0 int0 imf ef4 int0en=1 falling edge pulses of less than 2/fc [s] are eliminated as noise. pulses of 7/fc [s] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are considered to be signals. int1 int1 imf ef5 = 1 falling edge or rising edge pulses of less than 15/fc or 63/fc [s] are elimina- ted as noise. pulses of 49/fc or 193/fc [s] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are considered to be signals. int2 int2 imf ef8 = 1 falling edge or rising edge pulses of less than 7/fc [s] are eliminated as noise. pulses of 25/fc [s] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are considered to be signals. int3 int3 imf ef11 = 1 falling edge or rising edge pulses of less than 7/fc [s] are eliminated as noise. pulses of 25/fc [s] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are considered to be signals. int4 int4 imf + ef14 = 1 and il14er=0 falling edge, rising edge, falling and rising edge or h level pulses of less than 7/fc [s] are eliminated as noise. pulses of 25/fc [s] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are considered to be signals. int5 int5 imf ef15 = 1 and il15er=0 falling edge pulses of less than 2/fc [s] are eliminated as noise. pulses of 7/fc [s] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are considered to be signals. note 1: in normal1/2 or idle1/2 mode, if a signal with no noise is input on an external interrupt pin, it takes a maximum of "signal establishment time + 6/fs[s]" from the input signal's edge to set the interrupt latch. note 2: when int0en = "0", il4 is not set even if a falling edge is detected on the int0 pin input. note 3: when a pin with more than one function is used as an output and a change occurs in data or input/output status, an interrupt request signal is generated in a pseudo manner. in this case, it is necessary to perform appropriate processing such as disabling the interrupt enable flag. external interrupt control register eintcr 7 6 5 4 3 2 1 0 (0037h) int1nc int0en int4es int3es int2es int1es (initial value: 0000 000*) int1nc noise reject time select 0: pulses of less than 63/fc [s] are eliminated as noise 1: pulses of less than 15/fc [s] are eliminated as noise r/w int0en p00/ int0 pin configuration 0: p00 input/output port 1: int0 pin (port p00 should be set to an input mode) r/w int4 es int4 edge select 00: rising edge 01: falling edge 10: rising edge and falling edge 11: h level r/w int3 es int3 edge select 0: rising edge 1: falling edge r/w int2 es int2 edge select 0: rising edge 1: falling edge r/w int1 es int1 edge select 0: rising edge 1: falling edge r/w TMP86FH47AUG 3. interrupt control circuit 3.8 external interrupts page 40 note 1: fc: high-frequency clock [hz], *: dont care note 2: when the system clock frequency is switched between high and low or when the external interrupt control register (eintcr) is overwritten, the noise canceller may not operate normally. it is recommended that external interrupts are disabled using the interrupt enable register (eir). note 3: the maximum time from modifying int1nc until a noise reject time is changed is 2 6 /fc. note 4: in case reset pin is released while the state of int4 pin keeps "h" level, the external interrupt 4 request is not generated even if the int4 edge select is specified as "h" level. the rising edge is needed after reset pin is released. TMP86FH47AUG page 41 TMP86FH47AUG 3. interrupt control circuit 3.8 external interrupts page 42 4. special function register (sfr) the TMP86FH47AUG adopts the memory mapped i/o system, and all peripheral control and data transfers are performed through the special function register (sfr) or the data buffer register (dbr). the sfr is mapped on address 0000h to 003fh, dbr is mapped on address 0f80h to 0fffh. this chapter shows the arrangement of the special function register (sfr) and data buffer register (dbr) for TMP86FH47AUG. 4.1 sfr address read write 0000h p0dr 0001h p1dr 0002h p2dr 0003h p3dr 0004h p4dr 0005h reserved 0006h reserved 0007h reserved 0008h p0prd - 0009h reserved 000ah p2prd - 000bh reserved 000ch reserved 000dh p1cr 000eh p3cr 000fh p4cr 0010h tc1dral 0011h tc1drah 0012h tc1drbl 0013h tc1drbh 0014h tc1cr 0015h reserved 0016h tc3cr 0017h tc4cr 0018h ttreg3 0019h ttreg4 001ah pwreg3 001bh pwreg4 001ch adccr1 001dh adccr2 001eh adcdr2 - 001fh adcdr1 - 0020h uartsr uartcr1 0021h - uartcr2 0022h rdbuf tdbuf 0023h reserved 0024h reserved 0025h reserved TMP86FH47AUG page 43 address read write 0026h siocr1 0027h siosr 0028h siordb siotdb 0029h reserved 002ah reserved 002bh reserved 002ch reserved 002dh reserved 002eh reserved 002fh reserved 0030h reserved 0031h - stopcr 0032h reserved 0033h reserved 0034h - wdtcr1 0035h - wdtcr2 0036h tbtcr 0037h eintcr 0038h syscr1 0039h syscr2 003ah eirl 003bh eirh 003ch ill 003dh ilh 003eh intsel 003fh psw note 1: do not access reserved areas by the program. note 2: ? ; cannot be accessed. note 3: write-only registers and interrupt latches cannot use the read-modify-write instructions (bit manipulation instructions such as set, clr, etc. and logical operation instructions such as and, or, etc.). TMP86FH47AUG 4. special function register (sfr) 4.1 sfr page 44 4.2 dbr address read write 0f80h reserved : : : : 0f9fh reserved address read write 0fa0h reserved : : : : 0fbfh reserved address read write 0fc0h reserved : : : : 0fdfh reserved address read write 0fe0h reserved 0fe1h reserved 0fe2h reserved 0fe3h reserved 0fe4h reserved 0fe5h reserved 0fe6h reserved 0fe7h reserved 0fe8h reserved 0fe9h - flsstb 0feah spcr 0febh reserved 0fech reserved 0fedh reserved 0feeh reserved 0fefh reserved 0ff0h reserved 0ff1h reserved 0ff2h reserved 0ff3h reserved 0ff4h reserved 0ff5h reserved 0ff6h reserved 0ff7h reserved 0ff8h reserved 0ff9h reserved 0ffah reserved 0ffbh reserved 0ffch reserved 0ffdh reserved 0ffeh reserved TMP86FH47AUG page 45 address read write 0fffh flscr note 1: do not access reserved areas by the program. note 2: ? ; cannot be accessed. note 3: write-only registers and interrupt latches cannot use the read-modify-write instructions (bit manipulation instructions such as set, clr, etc. and logical operation instructions such as and, or, etc.). TMP86FH47AUG 4. special function register (sfr) 4.2 dbr page 46 5. time base timer (tbt) the time base timer generates time base for key scanning, dynamic displaying, etc. it also provides a time base timer interrupt (inttbt). 5.1 time base timer 5.1.1 configuration figure 5-1 time base timer configuration 5.1.2 control time base timer is controlled by time base timer control register (tbtcr). time base timer control register 7 6 5 4 3 2 1 0 tbtcr (0036h) (dvoen) (dvock) (dv7ck) tbten tbtck (initial value: 0000 0000) tbten time base timer enable / disable 0: disable 1: enable tbtck time base timer interrupt frequency select : [hz] normal1/2, idle1/2 mode slow1/2 sleep1/2 mode r/w dv7ck = 0 dv7ck = 1 000 fc/2 23 fs/2 15 fs/2 15 001 fc/2 21 fs/2 13 fs/2 13 010 fc/2 16 fs/2 8 - 011 fc/2 14 fs/2 6 - 100 fc/2 13 fs/2 5 - 101 fc/2 12 fs/2 4 - 110 fc/2 11 fs/2 3 - 111 fc/2 9 fs/2 - note 1: fc; high-frequency clock [hz], fs; low-frequency clock [hz], *; don't care TMP86FH47AUG page 47 fc/2 23 or fs/2 15 fc/2 21 or fs/2 13 fc/2 16 or fs/2 8 fc/2 14 or fs/2 6 fc/2 13 or fs/2 5 fc/2 12 or fs/2 4 fc/2 11 or fs/2 3 fc/2 9 or fs/2 tbtcr tbten tbtck 3 mpx source clock falling edge detector time base timer control register inttbt interrupt request idle0, sleep0 release request note 2: the interrupt frequency (tbtck) must be selected with the time base timer disabled (tbten = "0"). (the interrupt fre- quency must not be changed with the disable from the enable state.) both frequency selection and enabling can be performed simultaneously. example :set the time base timer frequency to fc/2 16 [hz] and enable an inttbt interrupt. ld (tbtcr) , 00000010b ; tbtck 010 ld (tbtcr) , 00001010b ; tbten 1 di ; imf 0 set (eirl) . 6 table 5-1 time base timer interrupt frequency ( example : fc = 16.0 mhz, fs = 32.768 khz ) tbtck time base timer interrupt frequency [hz] normal1/2, idle1/2 mode normal1/2, idle1/2 mode slow1/2, sleep1/2 mode dv7ck = 0 dv7ck = 1 000 1.91 1 1 001 7.63 4 4 010 244.14 128 - 011 976.56 512 - 100 1953.13 1024 - 101 3906.25 2048 - 110 7812.5 4096 - 111 31250 16384 - 5.1.3 function an inttbt ( time base timer interrupt ) is generated on the first falling edge of source clock ( the divider output of the timing generator which is selected by tbtck. ) after time base timer has been enabled. the divider is not cleared by the program; therefore, only the first interrupt may be generated ahead of the set interrupt period ( figure 5-2 ). figure 5-2 time base timer interrupt TMP86FH47AUG 5. time base timer (tbt) 5.1 time base timer page 48 source clock enable tbt interrupt period tbtcr 5.2 divider output ( dvo) approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric buzzer drive. divider output is from dvo pin. 5.2.1 configuration figure 5-3 divider output 5.2.2 control the divider output is controlled by the time base timer control register. time base timer control register 7 6 5 4 3 2 1 0 tbtcr (0036h) dvoen dvock (dv7ck) (tbten) (tbtck) (initial value: 0000 0000) dvoen divider output enable / disable 0: disable 1: enable r/w dvock divider output ( dvo) frequency selection: [hz] normal1/2, idle1/2 mode slow1/2 sleep1/2 mode r/w dv7ck = 0 dv7ck = 1 00 fc/2 13 fs/2 5 fs/2 5 01 fc/2 12 fs/2 4 fs/2 4 10 fc/2 11 fs/2 3 fs/2 3 11 fc/2 10 fs/2 2 fs/2 2 note:selection of divider output frequency (dvock) must be made while divider output is disabled (dvoen="0"). also, in other words, when changing the state of the divider output frequency from enabled (dvoen="1") to disable(dvoen="0"), do not change the setting of the divider output frequency. TMP86FH47AUG page 49 tbtcr output latch port output latch mpx dvoen tbtcr example :1.95 khz pulse output (fc = 16.0 mhz) setting port ld (tbtcr) , 00000000b ; dvock "00" ld (tbtcr) , 10000000b ; dvoen "1" table 5-2 divider output frequency ( example : fc = 16.0 mhz, fs = 32.768 khz ) dvock divider output frequency [hz] normal1/2, idle1/2 mode slow1/2, sleep1/2 mode dv7ck = 0 dv7ck = 1 00 1.953 k 1.024 k 1.024 k 01 3.906 k 2.048 k 2.048 k 10 7.813 k 4.096 k 4.096 k 11 15.625 k 8.192 k 8.192 k TMP86FH47AUG 5. time base timer (tbt) 5.2 divider output ( dvo) page 50 6. watchdog timer (wdt) the watchdog timer is a fail-safe system to detect rapidly the cpu malfunctions such as endless loops due to spurious noises or the deadlock conditions, and return the cpu to a system recovery routine. the watchdog timer signal for detecting malfunctions can be programmed only once as reset request or interrupt request. upon the reset release, this signal is initialized to reset request. when the watchdog timer is not used to detect malfunctions, it can be used as the timer to provide a periodic interrupt. note:care must be taken in system design since the watchdog timer functions are not be operated completely due to effect of disturbing noise. 6.1 watchdog timer configuration figure 6-1 watchdog timer configuration TMP86FH47AUG page 51 0034 h overflow wdt output internal reset binary counters wdtout writing clear code writing disable code wdten wdtt 2 0035 h watchdog timer control registers wdtcr1 wdtcr2 intwdt interrupt request interrupt request reset request reset release clock clear 1 2 controller q sr s r q selector fc/2 23 or fs/2 15 fc/2 21 or fs/2 13 fc/2 19 or fs/2 11 fc/2 17 or fs/2 9 6.2 watchdog timer control the watchdog timer is controlled by the watchdog timer control registers (wdtcr1 and wdtcr2). the watchdog timer is automatically enabled after the reset release. 6.2.1 malfunction detection methods using the watchdog timer the cpu malfunction is detected, as shown below. 1. set the detection time, select the output, and clear the binary counter. 2. clear the binary counter repeatedly within the specified detection time. if the cpu malfunctions such as endless loops or the deadlock conditions occur for some reason, the watchdog timer output is activated by the binary-counter overflow unless the binary counters are cleared. when wdtcr1 watchdog timer control register 1 wdtcr1 (0034h) 7 6 5 4 3 2 1 0 (atas) (atout) wdten wdtt wdtout (initial value: **11 1001) wdten watchdog timer enable/disable 0: disable (writing the disable code to wdtcr2 is required.) 1: enable write only wdtt watchdog timer detection time [s] normal1/2 mode slow1/2 mode write only dv7ck = 0 dv7ck = 1 00 2 25 /fc 2 17 /fs 2 17 /fs 01 2 23 /fc 2 15 /fs 2 15 fs 10 2 21 fc 2 13 /fs 2 13 fs 11 2 19 /fc 2 11 /fs 2 11 /fs wdtout watchdog timer output select 0: interrupt request 1: reset request write only note 1: after clearing wdtout to 0, the program cannot set it to 1. note 2: fc: high-frequency clock [hz], fs: low-frequency clock [hz], *: dont care note 3: wdtcr1 is a write-only register and must not be used with any of read-modify-write instructions. if wdtcr1 is read, a dont care is read. note 4: to activate the stop mode, disable the watchdog timer or clear the counter immediately before entering the stop mode. after clearing the counter, clear the counter again immediately after the stop mode is inactivated. note 5: to clear wdten, set the register in accordance with the procedures shown in 6.2.3 watchdog timer disable. watchdog timer control register 2 wdtcr2 (0035h) 7 6 5 4 3 2 1 0 (initial value: **** ****) wdtcr2 write watchdog timer control code 4eh: clear the watchdog timer binary counter (clear code) b1h: disable the watchdog timer (disable code) d2h: enable assigning address trap area others: invalid write only note 1: the disable code is valid only when wdtcr1 6.2.3 watchdog timer disable to disable the watchdog timer, set the register in accordance with the following procedures. setting the register in other procedures causes a malfunction of the micro controller. 1. set the interrupt master flag (imf) to 0. 2. set wdtcr2 to the clear code (4eh). 3. set wdtcr1 6.2.5 watchdog timer reset when a binary-counter overflow occurs while wdtcr1 6.3 address trap the watchdog timer control register 1 and 2 share the addresses with the control registers to generate address traps. watchdog timer control register 1 wdtcr1 (0034h) 7 6 5 4 3 2 1 0 atas atout (wdten) (wdtt) (wdtout) (initial value: **11 1001) atas select address trap generation in the internal ram area 0: generate no address trap 1: generate address traps (after setting atas to 1, writing the control code d2h to wdtcr2 is required) write only atout select operation at address trap 0: interrupt request 1: reset request watchdog timer control register 2 wdtcr2 (0035h) 7 6 5 4 3 2 1 0 (initial value: **** ****) wdtcr2 write watchdog timer control code and address trap area control code d2h: enable address trap area selection (atrap control code) 4eh: clear the watchdog timer binary counter (wdt clear code) b1h: disable the watchdog timer (wdt disable code) others: invalid write only 6.3.1 selection of address trap in internal ram (atas) wdtcr1 6.3.4 address trap reset while wdtcr1 TMP86FH47AUG 6. watchdog timer (wdt) 6.3 address trap page 58 7. i/o ports the TMP86FH47AUG have 5 parallel input/output ports (35 pins) as follows. primary function secondary functions port p0 8-bit i/o port external interrupt input, serial prom mode control input, serial and timer/counter input/output port p1 8-bit i/o port external interrupt input, timer/counter input/output, and divider output port p2 3-bit i/o port low-frequency resonator connections, external interrupt input, and stop mode release signal input port p3 8-bit i/o port analog input, and stop mode release signal input port p4 8-bit i/o port each output port contains a latch, which holds the output data. all input ports do not have latches, so the external input data should be externally held until the input data is read from outside or reading should be performed several times before processing. figure 7-1 shows input/output timing examples. external data is read from an i/o port in the s1 state of the read cycle during execution of the read instruction. this timing cannot be recognized from outside, so that transient input such as chattering must be processed by the program. output data changes in the s2 state of the write cycle during execution of the instruction which writes to an i/o port. note:the positions of the read and write cycles may vary, depending on the instruction. figure 7-1 input/output timing (example) TMP86FH47AUG page 59 ! " # ! " # ! " # $ % ! " # ! " # ! " # &' $ &' 7.1 port p0 (p07 to p00) port p0 is an 8-bit input/output port which is also used as an external interrupt input, serial prom mode control input, serial interface input/output and timer/counter input/output. when used as an input port or a secondary function pins, the respective output latch (p0dr) should be set to 1. when used as an output port, the respective p0dr bit should be set data. during reset, the output latch is initialized to 1. p0 port output latch (p0dr) and p0 port terminal input (p0prd) are located on their respective address. when read the output latch data, the p0dr should be read and when read the terminal input data, the p0prd register should be read. p00 port ( int0) can be configured as either an i/o port or as external interrupt input with int0en (bit 6 in eintcr). during reset, p00 port ( int0) is configured as an input port. figure 7-2 port p0 p0dr (0000h) r/w 7 6 5 4 3 2 1 0 p07 int4 p06 sck p05 si p04 so p03 txd p02 rxd boot p01 pwm4 tc4 pdo4 ppg4 p00 int0 (initial value: 1111 1111) p0prd (0008h) read only 7 6 5 4 3 2 1 0 p07 p06 p05 p04 p03 p02 p01 p00 TMP86FH47AUG 7. i/o ports 7.1 port p0 (p07 to p00) page 60 7.2 port p1 (p17 to p10) port p1 is an 8-bit input/output port which can be configured as an input or an output in one-bit unit under software control. input/output mode is specified by the corresponding bit in the port p1 input/output control register (p1cr). port p1 is configured as an input if its corresponding p1cr bit is cleared to 0, and as an output if its corresponding p1cr bit is set to 1. during reset, the p1cr is initialized to 0 and port p1 is input mode. the p1 output latches are also initialized to 0. port p1 is also used as an external interrupt input, a timer/counter input/output, and a divider output. when used as an input port, an external interrupt input or a timer/counter input, the corresponding bit of p1cr is cleared to 0. when used as a timer/counter output or divider output, the corresponding bit of p1cr is set to 1 and beforehand the corresponding output latch should be set to 1. data can be written into the output latch regardless of p1cr contents, therefore initial output data should be written into the output latch before setting p1cr. figure 7-3 port p1 p1dr (0001h) r/w 7 6 5 4 3 2 1 0 p17 p16 p15 int3 p14 ppg p13 dvo p12 int2 tc1 p11 int1 p10 pwm3 tc3 pdo3 (initial value: 0000 0000) p1cr (000dh) 7 6 5 4 3 2 1 0 (initial value: 0000 0000) p1cr i/o port for p1 port (specified for each bit) 0: input mode 1: output mode r/w note:ports set to the input mode read the pin states. ports set to the output mode read the output latch. when input pin and output pin exist in port p1 together, the contents of the output latch which is specified as an input mode may be rewritten by executing the bit manipulation instructions. TMP86FH47AUG page 61 7.3 port p2 (p22 to p20) port p2 is a 3-bit input/output port. it is also used as an external interrupt, a stop mode release signal input, and low-frequency crystal oscillator connection pins. when used as an input port or a secondary function pins, respective output latch (p2dr) should be set to 1. during reset, the p2dr is initialized to 1. a low-frequency crystal oscillator (32.768 khz) is connected to pins p21 (xtin) and p22 (xtout) in the dual- clock mode. in the single-clock mode, pins p21 and p22 can be used as normal input/output ports. it is recommended that pin p20 should be used as an external interrupt input, a stop mode release signal input, or an input port. if it is used as an output port, the interrupt latch is set on the falling edge of the output pulse. p2 port output latch (p2dr) and p2 port terminal input (p2prd) are located on their respective address. when read the output latch data, the p2dr should be read and when read the terminal input data, the p2prd register should be read. if a read instruction is executed for port p2, read data of bits 7 to 3 are unstable. figure 7-4 port p2 p2dr (0002h) r/w 7 6 5 4 3 2 1 0 p22 xtout p21 xtin p20 int5 stop (initial value: **** *111) p2prd (000ah) read only 7 6 5 4 3 2 1 0 p22 p21 p20 TMP86FH47AUG 7. i/o ports 7.3 port p2 (p22 to p20) page 62 ! " # $# % & % & % & 7.4 port p3 (p37 to p30) port p3 is an 8-bit input/output port which can be configured as an input or an output in one-bit unit under software control. port p3 is also used as an analog input, key on wake up input. input/output mode is specified by the corre- sponding bit in the port p3 input/output control register (p3cr), and adccr1 note:ports set to the input mode read the pin states. ports set to the output mode read the output latch. when input pin and output pin exist in port p3 together, the contents of the output latch which is specified as an input mode may be rewritten by executing the bit manipulation instructions. TMP86FH47AUG 7. i/o ports 7.4 port p3 (p37 to p30) page 64 7.5 port p4 (p47 to p40) port p4 is an 8-bit input/output port which can be configured as an input or an output in one-bit unit under software control. input/output mode is specified by the corresponding bit in the port p4 input/output control register (p4cr). port p4 is configured as an input if its corresponding p4cr bit is cleared to 0, and as an output if its corresponding p4cr bit is set to 1. during reset, the p4cr is initialized to 0 and port p4 is input mode. the p4 output latches are also initialized to 0. when used as an input port, the corresponding bit of p4cr is cleared to 0. when used as an output port, the corresponding bit of p4cr is set to 1. data can be written into the output latch regardless of p4cr contents, therefore initial output data should be written into the output latch before setting p4cr. figure 7-6 port p4 p4dr (0004h) r/w 7 6 5 4 3 2 1 0 p47 p46 p45 p44 p43 p42 p41 p40 (initial value: 0000 0000) p4cr (000fh) 7 6 5 4 3 2 1 0 (initial value: 0000 0000) p4cr i/o control for port p4 (specified for each bit) 0: input mode 1: output mode r/w note:ports set to the input mode read the pin states. ports set to the output mode read the output latch. when input pin and output pin exist in port p4 together, the contents of the output latch which is specified as an input mode may be rewritten by executing the bit manipulation instructions. TMP86FH47AUG page 65 TMP86FH47AUG 7. i/o ports 7.5 port p4 (p47 to p40) page 66 8. 16-bit timer/counter 1 (tc1) 8.1 configuration figure 8-1 timercounter 1 (tc1) TMP86FH47AUG page 67 :::? pin tc1 :w:?::? mett1 start capture clear source clock ppg output mode write to tc1cr 16-bit up-counter clear tc1drb selector tc1dra tc1cr tc1 control register match inttc1 interript tff1 acap1 tc1ck window mode set toggle q 2 toggle set clear q y a d b c s b a y s tc1s clear mppg1 ppg output mode internal reset s enable mcap1 s y a b tc1s 2 set clear command start decoder external trigger start edge detector note: function i/o may not operate depending on i/o port setting. for more details, see the chapter "i/o port". port (note) q pulse width measurement mode falling rising trigger external cmp 16-bit timer register a, b pulse width measurement mode port (note) fc/2 11, fs/2 3 fc/2 7 fc/2 3 8.2 timer/counter control the timercounter 1 is controlled by the timercounter 1 control register (tc1cr) and two 16-bit timer registers (tc1dra and tc1drb). timer register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tc1dra (0011h, 0010h) tc1drah (0011h) tc1dral (0010h) (initial value: 1111 1111 1111 1111) read/write tc1drb (0013h, 0012h) tc1drbh (0013h) tc1drbl (0012h) (initial value: 1111 1111 1111 1111) read/write (write enabled only in the ppg output mode) timercounter 1 control register tc1cr (0014h) 7 6 5 4 3 2 1 0 tff1 acap1 mcap1 mett1 mppg1 tc1s tc1ck tc1m read/write (initial value: 0000 0000) tff1 timer f/f1 control 0: clear 1: set r/w acap1 auto capture control 0 : auto-capture disable 1 : auto-capture enable r/w mcap1 pulse width measurement mode control 0 :double edge capture 1 : single edge capture mett1 external trigger timer mode control 0 : trigger start 1 : trigger start and stop mppg1 ppg output control 0 : continuous pulse generation 1 : one-shot tc1s tc1 start control timer extrig- ger event win- dow pulse ppg r/w 00: stop and counter clear o o o o o o 01: command start o - - - - o 10: rising edge start (ex-trigger/pulse/ppg) rising edge count (event) positive logic count (window) - o o o o o 11: falling edge start (ex-trigger/pulse/ppg) falling edge count (event) negative logic count (window) - o o o o o tc1ck tc1 source clock select [hz] normal1/2, idle1/2 mode divider slow, sleep mode r/w dv7ck = 0 dv7ck = 1 00 fc/2 11 fs/2 3 dv9 fs/2 3 01 fc/2 7 fc/2 7 dv5 - 10 fc/2 3 fc/2 3 dv1 - 11 external clock (tc1 pin input) tc1m tc1 operating mode se- lect 00: timer/external trigger timer/event counter mode 01: window mode 10: pulse width measurement mode 11: ppg (programmable pulse generate) output mode r/w note 1: fc: high-frequency clock [hz], fs: low-frequency clock [hz] note 2: the timer register consists of two shift registers. a value set in the timer register becomes valid at the rising edge of the first source clock pulse that occurs after the upper byte (tc1drah and tc1drbh) is written. therefore, write the lower byte and the upper byte in this order (it is recommended to write the register with a 16-bit access instruction). writing only the lower byte (tc1dral and tc1drbl) does not enable the setting of the timer register. TMP86FH47AUG 8. 16-bit timer/counter 1 (tc1) 8.2 timer/counter control page 68 note 3: to set the mode, source clock, ppg output control and timer f/f control, write to tc1cr during tc1s=00. set the timer f/f1 control until the first timer start after setting the ppg mode. note 4: auto-capture can be used only in the timer, event counter, and window modes. note 5: to set the timer registers, the following relationship must be satisfied. tc1dra > tc1drb > 1 (ppg output mode), tc1dra > 1 (other modes) note 6: set tff1 to 0 in the mode except ppg output mode. note 7: set tc1drb after setting tc1m to the ppg output mode. note 8: when the stop mode is entered, the start control (tc1s) is cleared to 00 automatically, and the timer stops. after the stop mode is exited, set the tc1s to use the timer counter again. note 9: use the auto-capture function in the operative condition of tc1. a captured value may not be fixed if it's read after the execution of the timer stop or auto-capture disable. read the capture value in a capture enabled condition. note 10: since the up-counter value is captured into tc1drb by the source clock of up-counter after setting tc1cr 8.3 function timercounter 1 has six types of operating modes: timer, external trigger timer, event counter, window, pulse width measurement, programmable pulse generator output modes. 8.3.1 timer mode in the timer mode, the up-counter counts up using the internal clock. when a match between the up-counter and the timer register 1a (tc1dra) value is detected, an inttc1 interrupt is generated and the up-counter is cleared. after being cleared, the up-counter restarts counting. setting tc1cr figure 8-2 timer mode timing chart TMP86FH47AUG page 71 match detect acap1 tc1drb tc1dra inttc1 interruput request source clock counter source clock counter ? (a) timer mode (b) auto-capture ? 7 6 345 0 timer start 12 3 2 1 4 0 counter clear capture n + 1 n n n m + 2 m + 1 m m capture m + 2 m + 1 n + 1 n m ? 1 m ? 1 m ? 2 n ? 1 n ? 1 n ? 1 8.3.2 external trigger timer mode in the external trigger timer mode, the up-counter starts counting by the input pulse triggering of the tc1 pin, and counts up at the edge of the internal clock. for the trigger edge used to start counting, either the rising or falling edge is defined in tc1cr figure 8-3 external trigger timer mode timing chart TMP86FH47AUG page 73 inttc1 interrupt request source clock up-counter tc1dra tc1 pin input inttc1 interrupt request source clock up-counter tc1dra tc1 pin input 0 at the rising edge (tc1s = 10) at the rising edge (tc1s = 10) (a) trigger start (mett1 = 0) count start match detect count start 0 1 2 3 4 2 3 n (b) trigger start and stop (mett1 = 1) count start count start 0 1 2 3 m 0 n n 0 count clear note: m < n count clear 1 2 3 1 n m ? 1 n ? 1 match detect count clear 8.3.3 event counter mode in the event counter mode, the up-counter counts up at the edge of the input pulse to the tc1 pin. either the rising or falling edge of the input pulse is selected as the count up edge in tc1cr 8.3.4 window mode in the window mode, the up-counter counts up at the rising edge of the pulse that is logical anded product of the input pulse to the tc1 pin (window pulse) and the internal source clock. either the positive logic (count up during high-going pulse) or negative logic (count up during low-going pulse) can be selected. when a match between the up-counter and the tc1dra value is detected, an inttc1 interrupt is generated and the up-counter is cleared. define the window pulse to the frequency which is sufficiently lower than the internal source clock programmed with tc1cr 8.3.5 pulse width measurement mode in the pulse width measurement mode, the up-counter starts counting by the input pulse triggering of the tc1 pin, and counts up at the edge of the internal clock. either the rising or falling edge of the internal clock is selected as the trigger edge in tc1cr example :duty measurement (resolution fc/2 7 [hz]) clr (inttc1sw). 0 ; inttc1 service switch initial setting address set to convert inttc1sw at each inttc1 ld (tc1cr), 00000110b ; sets the tc1 mode and source clock di ; imf= 0 set (eirl). 7 ; enables inttc1 ei ; imf= 1 ld (tc1cr), 00100110b ; starts tc1 with an external trigger at mcap1 = 0 : pinttc1: cpl (inttc1sw). 0 ; inttc1 interrupt, inverts and tests inttc1 service switch jrs f, sinttc1 ld a, (tc1drbl) ; reads tc1drb (high-level pulse width) ld w,(tc1drbh) ld (hpulse), wa ; stores high-level pulse width in ram reti sinttc1: ld a, (tc1drbl) ; reads tc1drb (cycle) ld w,(tc1drbh) ld (width), wa ; stores cycle in ram : reti ; duty calculation : vinttc1: dw pinttc1 ; inttc1 interrupt vector TMP86FH47AUG page 77 width hpulse tc1 pin inttc1 interrupt request inttc1sw figure 8-6 pulse width measurement mode TMP86FH47AUG 8. 16-bit timer/counter 1 (tc1) 8.3 function page 78 tc1drb inttc1 interrupt request interrupt request tc1 pin input counter internal clock (mcap1 = "1") 23 n count start count start trigger (tc1s = "10") 1 3 2 1 4 0 n 0 capture n - 1 tc1drb inttc1 tc1 pin input counter internal clock (mcap1 = "0") 12 n count start count start (tc1s = "10") 3 2 1 4 0 n capture capture n + 1 m - 2 n + 3 n + 2 n + 1 m - 1 m0 m [application] high-or low-level pulse width measurement [application] (1) cycle/frequency measurement (2) duty measurement (a) single-edge capture (b) double-edge capture 8.3.6 programmable pulse generate (ppg) output mode in the programmable pulse generation (ppg) mode, an arbitrary duty pulse is generated by counting performed in the internal clock. to start the timer, tc1cr example :after stopping ppg, setting the ppg pin to a high-level to restart ppg (fc = 16 mhz) setting port ld (tc1cr), 10000111b ; sets the ppg mode, selects the source clock ldw (tc1dra), 007dh ; sets the cycle (1 ms 2 7 /fc s = 007dh) ldw (tc1drb), 0019h ; sets the low-level pulse width (200 s 2 7 /fc = 0019h) ld (tc1cr), 10010111b ; starts the timer : : ld (tc1cr), 10000111b ; stops the timer ld (tc1cr), 10000100b ; sets the timer mode ld (tc1cr), 00000111b ; sets the ppg mode, tff1 = 0 ld (tc1cr), 00010111b ; starts the timer figure 8-7 ppg output TMP86FH47AUG 8. 16-bit timer/counter 1 (tc1) 8.3 function page 80 q r d ppg pin function output port output enable i/o port output latch shared with ppg output data output toggle set clear q tc1cr figure 8-8 ppg mode timing chart TMP86FH47AUG page 81 inttc1 tc1dra internal clock counter tc1drb tc1dra ppg pin output 0 inttc1 interrupt request interrupt request 12 m01 2 n m01 n 2 n n + 1 n + 1 m (a) continuous pulse generation (tc1s = 01) tc1drb trigger count start timer start counter internal clock tc1 pin input ppg pin output 0 1m n n n + 1 m 0 (b) one-shot pulse generation (tc1s = 10) match detect note: m > n note: m > n [application] one-shot pulse output TMP86FH47AUG 8. 16-bit timer/counter 1 (tc1) 8.3 function page 82 9. 8-bit timercounter (tc3, tc4) 9.1 configuration figure 9-1 8-bit timercounter 3, 4 TMP86FH47AUG page 83 8-bit up-counter decode en a y b s a b y c d e f g h s a y b s s a y b toggle q set clear 8-bit up-counter a b y c d e f g h s decode en toggle q set clear pwm mode pdo, ppg mode pdo mode pwm, ppg mode pwm mode pwm mode 16-bit mode 16-bit mode 16-bit mode 16-bit mode timer, event counter mode overflow overflow timer, event couter mode 16-bit mode clear clear fc/2 7 fc/2 5 fc/2 3 fc/2 fc fc/2 7 fc/2 5 fc/2 3 fc/2 fc pdo, pwm, ppg mode pdo, pwm mode 16-bit mode fc/2 11 or fs/2 3 fc/2 11 or fs/2 3 fs fs tc4cr tc3cr ttreg4 pwreg4 ttreg3 pwreg3 tc3 pin tc4 pin tc4s tc3s inttc3 interrupt request inttc4 interrupt request tff4 tff3 pdo 4 /pwm 4 / ppg 4 pin pdo 3 /pwm 3 / pin tc3ck tc4ck tc3m tc3s tff3 tc4m tc4s tff4 timer f/f4 timer f/f3 9.2 timercounter control the timercounter 3 is controlled by the timercounter 3 control register (tc3cr) and two 8-bit timer registers (ttreg3, pwreg3). timercounter 3 timer register ttreg3 (0018h) r/w 7 6 5 4 3 2 1 0 (initial value: 1111 1111) pwreg3 (001ah) r/w 7 6 5 4 3 2 1 0 (initial value: 1111 1111) note 1: do not change the timer register (ttreg3) setting while the timer is running. note 2: do not change the timer register (pwreg3) setting in the operating mode except the 8-bit and 16-bit pwm modes while the timer is running. timercounter 3 control register tc3cr (0016h) 7 6 5 4 3 2 1 0 tff3 tc3ck tc3s tc3m (initial value: 0000 0000) tff3 time f/f3 control (note 2,3) 0: 1: clear set r/w tc3ck operating clock selection [hz] (note 2,3,6) normal1/2, idle1/2 mode slow1/2 sleep1/2 mode r/w dv7ck = 0 dv7ck = 1 000 fc/2 11 fs/2 3 fs/2 3 001 fc/2 7 fc/2 7 - 010 fc/2 5 fc/2 5 - 011 fc/2 3 fc/2 3 - 100 fs fs fs 101 fc/2 fc/2 - 110 fc (note 8) fc (note 8) fc (note 8) 111 tc3 pin input tc3s tc3 start control (note 3) 0: 1: operation stop and counter clear operation start r/w tc3m tc3m operating mode select (note 2,3,7) 000: 001: 010: 011: 1**: 8-bit timer/event counter mode 8-bit programmable divider output (pdo) mode 8-bit pulse width modulation (pwm) output mode 16-bit mode (note 4,5) (each mode is selectable with tc4m.) reserved r/w note 1: fc: high-frequency clock [hz] fs: low-frequency clock[hz] note 2: do not change the tc3m, tc3ck and tff3 settings while the timer is running. note 3: to stop the timer operation (tc3s= 1 0), do not change the tc3m, tc3ck and tff3 settings. to start the timer operation (tc3s= 0 1), tc3m, tc3ck and tff3 can be programmed. note 4: to use the timercounter in the 16-bit mode, set the operating mode by programming tc4cr note 8: the clock "fc" can be selected as the source clock only in 8/16 bit pwm mode and in warming-up counter mode in slow or sleep mode. TMP86FH47AUG page 85 the timercounter 4 is controlled by the timercounter 4 control register (tc4cr) and two 8-bit timer registers (ttreg4 and pwreg4). timercounter 4 timer register ttreg4 (0019h) r/w 7 6 5 4 3 2 1 0 (initial value: 1111 1111) pwreg4 (001bh) r/w 7 6 5 4 3 2 1 0 (initial value: 1111 1111) note 1: do not change the timer register (ttreg4) setting while the timer is running. note 2: do not change the timer register (pwreg4) setting in the operating mode except the 8-bit and 16-bit pwm modes while the timer is running. timercounter 4 control register tc4cr (0017h) 7 6 5 4 3 2 1 0 tff4 tc4ck tc4s tc4m (initial value: 0000 0000) tff4 timer f/f4 control (note 2,3) 0: 1: clear set r/w tc4ck operating clock selection [hz] (note 2,3,7) normal1/2, idle1/2 mode slow1/2 sleep1/2 mode r/w dv7ck = 0 dv7ck = 1 000 fc/2 11 fs/2 3 fs/2 3 001 fc/2 7 fc/2 7 - 010 fc/2 5 fc/2 5 - 011 fc/2 3 fc/2 3 - 100 fs fs fs 101 fc/2 fc/2 - 110 fc (note 9) fc (note 9) - 111 tc4 pin input tc4s tc4 start control (note 3) 0: 1: operation stop and counter clear operation start r/w tc4m tc4m operating mode select (note 2,3,8) 000: 001: 010: 011: 100: 101: 110: 111: 8-bit timer/event counter mode 8-bit programmable divider output (pdo) mode 8-bit pulse width modulation (pwm) output mode reserved 16-bit timer/event counter mode warm-up counter mode 16-bit pulse width modulation (pwm) output mode 16-bit ppg mode r/w note 1: fc: high-frequency clock [hz] fs: low-frequency clock [hz] note 2: do not change the tc4m, tc4ck and tff4 settings while the timer is running. note 3: to stop the timer operation (tc4s= 1 0), do not change the tc4m, tc4ck and tff4 settings. to start the timer operation (tc4s= 0 1), tc4m, tc4ck and tff4 can be programmed. note 4: when tc4m= 1** (upper byte in the 16-bit mode), the source clock becomes the tc3 overflow signal regardless of the tc4ck setting. note 5: to use the timercounter in the 16-bit mode, select the operating mode by programming tc4m, where tc3cr note 7: the operating clock settings are limited depending on the timer operating mode. for the detailed descriptions, see table 9-1 and table 9-2. note 8: the timer register settings are limited depending on the timer operating mode. for the detailed descriptions, see table 9-3. note 9: the clock "fc" can be selected as the source clock only in 8 bit pwm mode. table 9-1 operating mode and selectable source clock (normal1/2 and idle1/2 modes) operating mode fc/2 11 or fs/2 3 fc/2 7 fc/2 5 fc/2 3 fs fc/2 fc tc3 pin input tc4 pin input 8-bit timer - - - - - 8-bit event counter - - - - - - - 8-bit pdo - - - - - 8-bit pwm - - 16-bit timer - - - - - 16-bit event counter - - - - - - - - warm-up counter - - - - - - - - 16-bit pwm - 16-bit ppg - - - - note 1: for 16-bit operations (16-bit timer/event counter, warm-up counter, 16-bit pwm and 16-bit ppg), set its source clock on lower bit (tc3ck). note 2: : available source clock table 9-2 operating mode and selectable source clock (slow1/2 and sleep1/2 modes) operating mode fc/2 11 or fs/2 3 fc/2 7 fc/2 5 fc/2 3 fs fc/2 fc tc3 pin input tc4 pin input 8-bit timer - - - - - - - - 8-bit event counter - - - - - - - 8-bit pdo - - - - - - - - 8-bit pwm - - - - - - - 16-bit timer - - - - - - - - 16-bit event counter - - - - - - - - warm-up counter - - - - - - - - 16-bit pwm - - - - - - 16-bit ppg - - - - - - - note 1: for 16-bit operations (16-bit timer/event counter, warm-up counter, 16-bit pwm and 16-bit ppg), set its source clock on lower bit (tc3ck). note 2: : available source clock TMP86FH47AUG page 87 table 9-3 constraints on register values being compared operating mode register value 8-bit timer/event counter 1 (ttregn) 255 8-bit pdo 1 (ttregn) 255 8-bit pwm 2 (pwregn) 254 16-bit timer/event counter 1 (ttreg4, 3) 65535 warm-up counter 256 (ttreg4, 3) 65535 16-bit pwm 2 (pwreg4, 3) 65534 16-bit ppg 1 (pwreg4, 3) < (ttreg4, 3) 65535 and (pwreg4, 3) + 1 < (ttreg4, 3) note:n = 3 to 4 TMP86FH47AUG 9. 8-bit timercounter (tc3, tc4) 9.2 timercounter control page 88 9.3 function the timercounter 3 and 4 have the 8-bit timer, 8-bit event counter, 8-bit programmable divider output (pdo), 8- bit pulse width modulation (pwm) output modes. the timercounter 3 and 4 (tc3, 4) are cascadable to form a 16- bit timer. the 16-bit timer has the operating modes such as the 16-bit timer, 16-bit event counter, warm-up counter, 16-bit pulse width modulation (pwm) output and 16-bit programmable pulse generation (ppg) modes. 9.3.1 8-bit timer mode (tc3 and 4) in the timer mode, the up-counter counts up using the internal clock. when a match between the up-counter and the timer register j (ttregj) value is detected, an inttcj interrupt is generated and the up-counter is cleared. after being cleared, the up-counter restarts counting. note 1: in the timer mode, fix tcjcr figure 9-2 8-bit timer mode timing chart (tc4) 9.3.2 8-bit event counter mode (tc3, 4) in the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the tcj pin. when a match between the up-counter and the ttregj value is detected, an inttcj interrupt is generated and the up-counter is cleared. after being cleared, the up-counter restarts counting at the falling edge of the input pulse to the tcj pin. two machine cycles are required for the low- or high-level pulse input to the tcj pin. therefore, a maximum frequency to be supplied is fc/2 4 hz in the normal1/2 or idle1/2 mode, and fs/2 4 hz in the slow1/2 or sleep1/2 mode. note 1: in the event counter mode, fix tcjcr example :generating 1024 hz pulse using tc4 (fc = 16.0 mhz) setting port ld (ttreg4), 3dh ; 1/1024 2 7 /fc 2 = 3dh ld (tc4cr), 00010001b ; sets the operating clock to fc/2 7 , and 8-bit pdo mode. ld (tc4cr), 00011001b ; starts tc4. note 1: in the programmable divider output mode, do not change the ttregj setting while the timer is running. since ttregj is not in the shift register configuration in the programmable divider output mode, the new value programmed in ttregj is in effect immediately after programming. therefore, if ttregj is changed while the timer is running, an expected operation may not be obtained. note 2: when the timer is stopped during pdo output, the pdoj pin holds the output status when the timer is stopped. to change the output status, program tcjcr figure 9-4 8-bit pdo mode timing chart (tc4) TMP86FH47AUG 9. 8-bit timercounter (tc3, tc4) 9.3 function page 92 12 0 n 0 n 0 n 0 n 0 1 2 2 1 2 1 2 3 1 0 n ? internal source clock counter match detect match detect match detect match detect held at the level when the timer is stopped set f/f write of "1" tc4cr 9.3.4 8-bit pulse width modulation (pwm) output mode (tc3, 4) this mode is used to generate a pulse-width modulated (pwm) signals with up to 8 bits of resolution. the up- counter counts up using the internal clock. when a match between the up-counter and the pwregj value is detected, the logic level output from the timer f/fj is switched to the opposite state. the counter continues counting. the logic level output from the timer f/ fj is switched to the opposite state again by the up-counter overflow, and the counter is cleared. the inttcj interrupt request is generated at this time. since the initial value can be set to the timer f/fj by tcjcr figure 9-5 8-bit pwm mode timing chart (tc4) TMP86FH47AUG 9. 8-bit timercounter (tc3, tc4) 9.3 function page 94 1 0 nn+1 ff 0 n n+1 ff 0 1 m m+1 ff 0 1 1 p n ? internal source clock counter m p m p n ? shift registar shift shift shift shift match detect match detect one cycle period match detect match detect n m p n tc4cr 9.3.5 16-bit timer mode (tc3 and 4) in the timer mode, the up-counter counts up using the internal clock. the timercounter 3 and 4 are cascadable to form a 16-bit timer. when a match between the up-counter and the timer register (ttreg3, ttreg4) value is detected after the timer is started by setting tc4cr figure 9-6 16-bit timer mode timing chart (tc3 and tc4) 9.3.6 16-bit event counter mode (tc3 and 4) in the event counter mode, the up-counter counts up at the falling edge to the t c3 pin. the timercounter 3 and 4 are cascadable to form a 16-bit event counter. when a match between the up-counter and the timer register (ttreg3, ttreg4) value is detected after the timer is started by setting tc4cr since pwreg4 and 3 in the pwm mode are serially connected to the shift register, the values set to pwreg4 and 3 can be changed while the timer is running. the values set to pwreg4 and 3 during a run of the timer are shifted by the inttcj interrupt request and loaded into pwreg4 and 3. while the timer is stopped, the values are shifted immediately after the programming of pwreg4 and 3. set the lower byte (pwreg3) and upper byte (pwreg4) in this order to program pwreg4 and 3. (programming only the lower or upper byte of the register should not be attempted.) if executing the read instruction to pwreg4 and 3 during pwm output, the values set in the shift register is read, but not the values set in pwreg4 and 3. therefore, after writing to the pwreg4 and 3, reading data of pwreg4 and 3 is previous value until inttc4 is generated. for the pin used for pwm output, the output latch of the i/o port must be set to 1. note 1: in the pwm mode, program the timer register pwreg4 and 3 immediately after the inttc4 interrupt request is generated (normally in the inttc4 interrupt service routine.) if the programming of pwregj and the interrupt request occur at the same time, an unstable value is shifted, that may result in generation of pulse different from the programmed value until the next inttc4 interrupt request is generated. note 2: when the timer is stopped during pwm output, the pwm 4 pin holds the output status when the timer is stopped. to change the output status, program tc4cr figure 9-7 16-bit pwm mode timing chart (tc3 and tc4) TMP86FH47AUG 9. 8-bit timercounter (tc3, tc4) 9.3 function page 98 1 0 an an+1 ffff 0 an an+1 ffff 0 1 bm bm+1 ffff 0 bm cp b c 1 1 cp n a an ? ? ? internal source clock 16-bit shift register shift shift shift shift counter match detect match detect one cycle period match detect match detect an bm cp an m p tc4cr 9.3.8 16-bit programmable pulse generate (ppg) output mode (tc3 and 4) this mode is used to generate pulses with up to 16-bits of resolution. the timer counter 3 and 4 are cascadable to enter the 16-bit ppg mode. the counter counts up using the internal clock or external clock. when a match between the up-counter and the timer register (pwreg3, pwreg4) value is detected, the logic level output from the timer f/f4 is switched to the opposite state. the counter continues counting. the logic level output from the timer f/f4 is switched to the opposite state again when a match between the up-counter and the timer register (ttreg3, ttreg4) value is detected, and the counter is cleared. the inttc4 interrupt is generated at this time. two machine cycles are required for the high- or low-level pulse input to the tc3 pin. therefore, a maximum frequency to be supplied is fc/2 4 hz in the normal1/2 or idle1/2 mode, and fs/2 4 to in the slow1/2 or sleep1/2 mode. since the initial value can be set to the timer f/f4 by tc4cr figure 9-8 16-bit ppg mode timing chart (tc3 and tc4) TMP86FH47AUG 9. 8-bit timercounter (tc3, tc4) 9.3 function page 100 1 0 mn mn+1 qr-1 mn qr-1 1 mn mn+1 mn+1 0 qr 0 qr 1 0 internal source clock counter write of "0" match detect match detect match detect mn mn mn match detect match detect ? n m ? ? r q ? held at the level when the timer stops f/f clear tc4cr 9.3.9 warm-up counter mode in this mode, the warm-up period time is obtained to assure oscillation stability when the system clocking is switched between the high-frequency and low-frequency. the timer counter 3 and 4 are cascadable to form a 16- bit timercounter. the warm-up counter mode has two types of mode; switching from the high-frequency to low- frequency, and vice-versa. note 1: in the warm-up counter mode, fix tcicr 9.3.9.2 high-frequency warm-up counter mode (slow1 slow2 normal2 normal1) in this mode, the warm-up period time from a stop of the high-frequency clock fc to the oscillation stability is obtained. before starting the timer, set syscr2 10. synchronous serial interface (sio) the serial interfaces connect to an external device via si, so, and sck pins. when these pins are used as serial interface, the output latches for each port should be set to "1". 10.1 configuration figure 10-1 synchronous serial interface (sio) TMP86FH47AUG page 103 interrupt internal clock input to bus shift register on transmitter shift register on receiver (serial data output) control circuit shift clock internal data bus port (note) (serial data output) port (note) (serial data input) port (note) note: set the register of port correctly for the port assigned as serial interface pins. for details, see the description of the input/output port control register. msb/lsb selection so pin si pin siotdb siordb sck pin intsio siocr1 siosr 10.2 control the sio is controlled using the serial interface control register (siocr1). the operating status of the serial interface can be inspected by reading the status register (siocr1). serial interface control register siocr1 (0026h) 7 6 5 4 3 2 1 0 sios sioinh siom siodir sck (initial value: 0000 0000) sios specify start/stop of transfer 0: stop 1: start r/w sioinh forcibly stops transfer (note 1) 0: - 1: forcibly stop (automatically cleared to "0" after stopping) siom selects transfer mode 00: transmit mode 01: receive mode 10: transmit/receive mode 11: reserved siodir selects direction of transfer 0: msb (transfer beginning with bit7) 1: lsb (transfer beginning with bit0) sck selects serial clock normal1/2 or idle1/2 modes slow/sleep mode tbtcr serial interface status register siosr (0027h) 7 6 5 4 3 2 1 0 siof sef txf rxf txerr rxerr (initial value: 0010 00**) siof serial transfer operation status monitor 0: transfer finished 1: transfer in progress read only sef number of clocks monitor 0: 8 clocks 1: 1 to 7 clocks txf transmit buffer empty flag 0: data exists in transmit buffer 1: no data exists in transmit buffer rxf receive buffer full flag 0: no data exists in receive buffer 1: data exists in receive buffer txerr transfer operation error flag read 0: - (no error exist) 1: transmit buffer under run occurs in an external clock mode write 0: clear the flag 1: - (a write of "1" to this bit is ignored) r/w rxerr receive operation error flag read 0: - (no error exist) 1: receive buffer over run occurs in an external clock mode write 0: clear the flag 1: - (a write of "1" to this bit is ignored) note 1: the operation error flag (txerr and rxerr) are not automatically cleared by stopping transfer with siocr1 10.3 function 10.3.1 serial clock 10.3.1.1 clock source the serial clock can be selected by using siocr1 (2) external clock when an external clock is selected by setting siocr1 10.3.2 transfer bit direction transfer data direction can be selected by using siocr1 (2) lsb receive mode lsb receive mode is selected by setting siocr1 (2) during the transmit operation when data is written to siotdb, siosr |